UPD78F9234MC-5A4-A Renesas Electronics America, UPD78F9234MC-5A4-A Datasheet
UPD78F9234MC-5A4-A
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UPD78F9234MC-5A4-A Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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User’s Manual 78K0S/KB1+ 8-bit Single-Chip Microcontrollers μ PD78F9232 μ PD78F9232(A) μ PD78F9232(A2) Document No. U17446EJ5V0UD00 (5th edition) Date Published November 2009 NS 2005 Printed in Japan μ PD78F9234 μ PD78F9234(A) μ PD78F9234(A2) ...
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User’s Manual U17446EJ5V0UD ...
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, ...
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Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a ...
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Target Readers This manual is intended for user engineers who wish to understand the functions of the 78K0S/KB1+ in order to design and develop its application systems and programs. The target devices are the following subseries products. 78K0S/KB1+: PD78F9232, 78F9234, ...
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Conventions Related Documents Documents Related to Devices 78K0S/KB1+ User’s Manual 78K/0S Series Instructions User’s Manual <R> Documents Related to Development Software Tools (User’s Manuals) RA78K0S Ver.2.00 Assembler Package CC78K0S Ver.2.00 C Compiler SM+ System Simulator ID78K0S-QB Ver.3.00 Integrated Debugger PM+ ...
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Other Related Documents SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See ...
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CHAPTER 1 OVERVIEW.........................................................................................................................14 1.1 Features .........................................................................................................................................14 1.2 Ordering Information....................................................................................................................15 1.3 Pin Configuration (Top View) ......................................................................................................16 1.4 78K0S/Kx1+ Product Lineup........................................................................................................18 1.5 Block Diagram...............................................................................................................................19 1.6 Functional Outline ........................................................................................................................20 CHAPTER 2 PIN FUNCTIONS ...............................................................................................................21 2.1 Pin Function List...........................................................................................................................21 2.2 Pin Functions ................................................................................................................................23 2.2.1 ...
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Register indirect addressing.............................................................................................................. 49 3.4.6 Based addressing ............................................................................................................................. 50 3.4.7 Stack addressing............................................................................................................................... 51 CHAPTER 4 PORT FUNCTIONS........................................................................................................... 52 4.1 Functions of Ports........................................................................................................................ 52 4.2 Port Configuration........................................................................................................................ 54 4.2.1 Port 0 ................................................................................................................................................ 55 4.2.2 Port 2 ................................................................................................................................................ 56 4.2.3 Port ...
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Configuration of 8-bit Timer 80 .................................................................................................130 7.3 Register Controlling 8-bit Timer 80...........................................................................................132 7.4 Operation of 8-bit Timer 80 ........................................................................................................133 7.4.1 Operation as interval timer ..............................................................................................................133 7.5 Notes on 8-bit Timer 80 ..............................................................................................................135 CHAPTER 8 8-BIT TIMER H1 .............................................................................................................136 8.1 ...
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CHAPTER 12 MULTIPLIER ..................................................................................................................220 12.1 Multiplier Function ...................................................................................................................220 12.2 Multiplier Configuration...........................................................................................................220 12.3 Multiplier Control Register ......................................................................................................222 12.4 Multiplier Operation .................................................................................................................223 CHAPTER 13 INTERRUPT FUNCTIONS ............................................................................................225 13.1 Interrupt Function Types.........................................................................................................225 13.2 Interrupt Sources and Configuration .....................................................................................226 13.3 Interrupt Function Control Registers ...
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Functional Outline ....................................................................................................................273 19.4 Writing with Flash Memory Programmer ...............................................................................274 19.5 Programming Environment .....................................................................................................275 19.6 Pin Connection on Board.........................................................................................................277 19.6.1 X1 and X2 pins ..............................................................................................................................277 19.6.2 RESET pin.....................................................................................................................................278 19.6.3 Port pins ........................................................................................................................................279 19.6.4 Power supply.................................................................................................................................279 19.7 On-Board and Off-Board ...
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APPENDIX A DEVELOPMENT TOOLS ..............................................................................................375 A.1 Software Package ......................................................................................................................378 A.2 Language Processing Software ...............................................................................................378 A.3 Flash Memory Writing Tools.....................................................................................................379 A.3.1 When using flash memory programmer PG-FP5 and FL-PR5........................................................ 379 A.3.2 When using on-chip debug emulator with programming function QB-MINI2................................... 379 ...
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Features O 78K0S CPU core O ROM and RAM capacities Item Part number μ PD78F9232 4 KB μ PD78F9234 Minimum instruction execution time: 0.2 O Clock • High-speed system clock … Selected from the following three ...
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O Assembler and C language supported O Enhanced development environment • Support for full-function emulator (IECUBE), simplified emulator (MINICUBE2), and simulator O Supply voltage ∗ Use these products in the following voltage range because the detection voltage (V ...
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Pin Configuration (Top View) • 30-pin plastic SSOP P123 P121/X1 P122/X2 P34/RESET P31/TI010/TO00/INTP2 P30/TI000/INTP0 Caution Connect the AV pin • 32-pin plastic SDIP P23/ANI3 P22/ANI2 P21/ANI1 P20/ANI0 AV REF P120 P03 P02 ...
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Pin Name ANI0 to ANI3: Analog input AV : Analog Power Supply, REF Analog Reference Voltage, Power Supply for P20 to P23 AV : Analog ground SS INTP0 to INTP3: External interrupt input P00 to P03: Port 0 P20 to ...
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Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number Item Number of pins <R> Internal Flash memory memory RAM Supply voltage Minimum instruction execution time System clock (oscillation frequency) Clock for TMH1 and ...
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Block Diagram TO00/TI010/P31 16-bit timer/ event counter 00 TI000/P30 8-bit timer 80 TOH1/P42 8-bit timer H1 Low-speed internal oscillator Watchdog timer RxD6/P44 Serial interface UART6 TxD6/P43 ANI0/P20 to 4 ANI3/P23 A/D converter AV REF AV SS INTP0/P30 INTP1/P43 Interrupt ...
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Functional Outline Item Internal Flash memory 4 KB memory High-speed RAM 256 bytes Memory space input clock (oscillation frequency) Crystal/ceramic/external clock input: 10 MHz (V Internal High speed (oscillation Internal oscillation: 8 MHz (TYP.) oscillation frequency) ...
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Pin Function List (1) Port pins Pin Name I/O P00 to P03 I/O Port 0. 4-bit I/O port. Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting software. ...
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Non-port pins Pin Name I/O INTP0 Input External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified INTP1 INTP2 INTP3 RxD6 Input Serial data input for asynchronous serial ...
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Pin Functions 2.2.1 P00 to P03 (Port 0) P00 to P03 function as a 4-bit I/O port. P00 to P03 can be set to input or output in 1-bit units using port mode register 0 (PM0). Use of an ...
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TO00 This pin outputs a signal from 16-bit timer/event counter 00. 2.2.4 P40 to P47 (Port 4) P40 to P47 constitute an 8-bit I/O port, port 4. In addition to I/O port pins, P41 to P44 also have functions ...
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X1 and X2 These pins connect an oscillator to oscillate the X1 input clock. X1 and X2 also function as the P121 and P122 pins, respectively. For settings of alternate function, refer to CHAPTER 18 OPTION BYTE. Supply an ...
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Pin I/O Circuits and Connection of Unused Pins Table 2-1 shows I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1. Table 2-1. ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 3-C V P-ch Data N-ch V Type 8-A Pull up enable V DD Data P-ch Output N-ch disable V SS CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 11 ...
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Memory Space The 78K0S/KB1+ can access memory space. Figures 3-1 and 3-2 show the memory maps Special function registers ...
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Figure 3-2. Memory Map ( Special function registers Internal high-speed RAM Data memory space 2 ...
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Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KB1+ provides the following internal ROMs (or flash memory) containing the following capacities. Part ...
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Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3). 3.1.4 Data memory addressing The 78K0S/KB1+ is provided with a wide range of addressing ...
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Figure 3-4. Data Memory Addressing ( Special function registers (SFR) 256 8 bits Internal high-speed ...
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Processor Registers The 78K0S/KB1+ provides the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, ...
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Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data to Be Saved to Stack Memory PUSH rp instruction Lower half register pairs Upper half register pairs SP Figure 3-9. Data to ...
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General-purpose registers A general-purpose register consists of eight 8-bit registers ( and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a ...
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Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose ...
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Address Symbol 7 6 FF00H − − − FF01H FF02H FF03H FF04H P4 P47 P46 − − − FF05H to FF0BH FF0CH P12 0 0 FF0DH P13 0 0 − ...
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Address Symbol 7 FF34H PU4 PU47 − − FF35H to FF3BH FF3CH PU12 0 − − FF3DH to FF47H FF48H WDTM 0 − FF49H WDTE FF50H LVIM <LVI ON> FF51H LVIS 0 − − FF52H, FF53H FF54H RESF 0 ...
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Address Symbol 7 6 FF84H PMC2 0 0 − − − FF85H to FF8BH FF8CH ISC 0 0 − − − FF8DH to FF8FH FF90H ASIM6 <POW <TXE6> <RXE6> ER6> − − − FF91H − − FF92H RXB6 FF93H ...
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Address Symbol 7 − FFD0H MRA0 − FFD1H MRB0 FFD2H MULC0 0 − − FFD3H to FFDFH FFE0H IF0 <ADIF> FFE1H IF1 0 − − FFE2H, FFE3H FFE4H MK0 <ADM K> FFE5H MK1 1 − − FFE6H to FFEBH ...
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Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions ...
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Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration ...
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Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H ...
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Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction ...
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Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing ...
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Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt ...
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Functions of Ports The 78K0S/KB1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports ...
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Pin Name I/O P00 to P03 I/O Port 0. 4-bit I/O port. Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected by setting software. P20 to P23 I/O Port 2. 4-bit I/O ...
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Port Configuration Ports consist of the following hardware units. Item Control registers Port mode registers (PM0, PM2, PM3, PM4, PM12) Port registers (P0, P2, P3, P4, P12, P13) Port mode control register 2 (PMC2) Pull-up resistor option registers (PU0, ...
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Port 0 Port 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 0 (PM0). When the P00 to P03 ...
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Port 2 Port 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 ...
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Port 3 Pins P30 to P33 constitute a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 3 (PM3). When the P30 ...
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WR PU PU3 PU31 Alternate function RD WR PORT P3 Output latch (P31 PM3 PM31 Alternate function PU3: Pull-up resistor option register 3 P3: Port register 3 PM3: Port mode register 3 RD: Read signal WR : Write ...
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Figure 4-6. Block Diagram of P32 and P33 WR PU PU3 PU32, PU33 RD WR PORT P3 Output latch (P32, P33 PM3 PM32, PM33 PU3: Pull-up resistor option register 3 P3: Port register 3 PM3: Port mode register ...
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Also, since the option byte is referenced after the reset release, if low level is input to the RESET pin before the referencing, then the reset state is not released. When it is used as an input port pin, connect ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P41 and P44 WR PU PU4 PU41, PU44 Alternate function RD WR PORT P4 Output latch (P41, P44 PM4 PM41, PM44 PU4: Pull-up resistor option register 4 P4: Port ...
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WR PU PU4 PU42 RD WR PORT P4 Output latch (P42 PM4 PM42 Alternate function PU4: Pull-up resistor option register 4 P4: Port register 4 PM4: Port mode register 4 RD: Read signal WR : Write signal 62 ...
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WR PU PU4 PU43 Alternate function RD WR PORT P4 Output latch (P43 PM4 PM43 Alternate function PU4: Pull-up resistor option register 4 P4: Port register 4 PM4: Port mode register 4 RD: Read signal WR : Write ...
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External clock input The P121 pin is used as the X1 pin to input an external clock, and therefore it cannot be used as an I/O port pin. The P122 pin can be used as an I/O port pin. ...
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Figure 4-13. Block Diagram of P121 and P122 RD WR PORT P12 Output latch (P121, P122 PM12 PM121, PM122 PM12: Port mode register 12 P12: Port register 12 RD: Read signal WR : Write signal 4.2.6 Port 13 ...
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Registers Controlling Port Functions The ports are controlled by the following four types of registers. Port mode registers (PM0, PM2, PM3, PM4, PM12) Port registers (P0, P2, P3, P4, P12, P13) Port mode control register 2 (PMC2) Pull-up resistor ...
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Port mode registers (PM0, PM2, PM3, PM4, PM12) These registers are used to set the corresponding port to the input or output mode in 1-bit units. Each port mode register can be set by a 1-bit or 8-bit memory ...
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Port registers (P0, P2, P3, P4, P12, P13) These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin ...
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Port mode control register 2 (PMC2) This register specifies the port mode or A/D converter mode. Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units. PMC2 is set ...
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Pull-up resistor option registers (PU0, PU2, PU3, PU4, and PU12) These registers are used to specify whether an on-chip pull-up resistor is connected to P00 to P03, P20 to P23, P30 to P33, P40 to P47, P120, and P123. ...
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Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the ...
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CHAPTER 5 CLOCK GENERATORS 5.1 Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation ...
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Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Control registers Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillation stabilization ...
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Figure 5-1. Block Diagram of Clock Generators Oscillation stabilization time select register (OSTS) OSTS1 OSTS0 System clock oscillation stabilization time counter STOP Watchdog timer System clock Note oscillator X1/P121 Crystal/ceramic oscillation X2/P122 X 2 External clock input ...
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Registers Controlling Clock Generators The clock generators are controlled by the following four registers. Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillation stabilization time select register (OSTS) (1) Processor clock ...
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The fastest instruction of the 78K0S/KB1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-2. CPU Table 5-2. Relationship Between CPU Clock ...
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Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the ...
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System Clock Oscillators The following three types of system clock oscillators are available. High-speed internal oscillator: Crystal/ceramic oscillator: External clock input circuit: 5.4.1 High-speed internal oscillator The 78K0S/KB1+ includes a high-speed internal oscillator (8 MHz (TYP.)). If the high-speed ...
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Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (c) Wiring near high fluctuating current CHAPTER 5 CLOCK ...
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Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched 5.4.3 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. If external clock input is selected by ...
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Operation of CPU Clock Generator A clock ( supplied to the CPU from the system clock (f CPU oscillators. High-speed internal oscillator: Crystal/ceramic oscillator: External clock input circuit: The system clock oscillator is selected by the option ...
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The internal reset signal is generated by the power-on-clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then ...
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Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator ( RESET H Internal reset System clock CPU clock System clock is selected. (Operation stops Notes 1. Operation stop time is 276 s (MIN.), 544 s (TYP.), and ...
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Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation Interrupt HALT Remark PCC: Processor clock control register PPCC: Preprocessor clock control register (3) External clock input circuit If external clock input is selected by the option byte, the following ...
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CHAPTER 5 CLOCK GENERATORS Figure 5-12. Timing of Default Start by External Clock Input ( RESET H Internal reset System clock CPU clock Option byte is read. System clock is selected. (Operation stops Note Operation stop time is ...
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Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. Clock to peripheral hardware (f XP Low-speed internal oscillation clock (f (1) Clock to peripheral hardware The clock ...
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Figure 5-14. Status Transition of Low-Speed Internal Oscillation Can be stopped Clock source of WDT is selected Note by software Low-speed internal oscillator can be stopped LSRSTOP = 1 Low-speed internal oscillator stops Note The clock source of the watchdog ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. • Number of counts: ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-bit Timer/Event Counter 00 Item Timer counter Register Timer input Timer output Control registers ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 • When CR000 is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the TI000 or ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Caution 7. Changing the CR000 setting during TM00 operation may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare register during timer operation. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 5. If the register read period and the input of the capture trigger conflict when CR010 is used as a capture register, the capture trigger input takes precedence and the read data is ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H R/W Symbol TMC00 TMC003 TMC003 TMC002 TMC001 Operating mode ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction. Generation of reset signal sets ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid edges. PRM00 is set by a 1-bit ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. Always set data to PRM00 after stopping the timer operation the valid edge of the TI000 pin set as the count clock, do not set the clear/start ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Control Register Settings for Interval Timer Operation (a) Capture/compare control register 00 (CRC00 CRC00 ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 (c) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-12. Timing of Interval Timer Operation t Count clock TM00 count value 0000H 0001H Timer operation enabled CR000 N INTTM000 Remark Interval time = ( × 0001H to ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-15. External Event Counter Configuration Diagram f Noise eliminator XP Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH. Figure 6-16. External ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Pulse width measurement with free-running counter and one capture register Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-19. Configuration Diagram for Pulse Width Measurement by Free-Running Counter TI000/INTP0/P30 Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter and ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode possible to simultaneously measure the pulse widths of the two signals input ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-22. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock 0000H 0001H TM00 count value TI000 pin input CR010 capture value INTTM010 TI010 pin input CR000 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00 CRC00 (b) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H TI000 pin input CR010 capture value CR000 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart (a) Capture/compare control register 00 (CRC00 CRC00 (b) Prescaler mode register 00 (PRM00) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-27 for the set ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 OSPT00 OSPE00 TOC004 LVS00 TOC00 0/1 (d) 16-bit timer mode control ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-29 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Control Register Settings for PPG Output Operation (a) Capture/compare control register 00 (CRC00 CRC00 (b) 16-bit timer output control register 00 (TOC00) 7 OSPT00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Configuration Diagram of PPG Output Noise TI000/INTP0/P30 eliminator f XP Figure 6-31. PPG Output Operation Timing Count clock TM00 count value N ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Control Register Settings for One-Shot Pulse Output with Software Trigger ES110 ES100 ES010 PRM00 0/1 0/1 (b) Capture/compare control register 00 (CRC00 CRC00 (c) 16-bit timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock TM00 count 0000H 0001H CR010 set value N CR000 set value M OSPT00 INTTM010 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Control Register Settings for One-Shot Pulse Output with External Trigger ES110 ES100 ES010 PRM00 0/1 0/1 0 (b) Capture/compare control register 00 (CRC00 CRC00 (c) 16-bit ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-35. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) t Count clock TM00 count value 0000H 0001H CR010 set ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (1) Timer start errors An error one clock may occur in the time required for a match signal to be generated after timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Capture register data retention The value of 16-bit timer capture/compare register 0n0 (CR0n0) after 16-bit timer/event counter 00 has stopped is not guaranteed. Remark (5) Setting of 16-bit timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (12) One-shot pulse output with external trigger <1> Do not input the external trigger again while the one-shot pulse is being output. To output the one-shot pulse again, wait until the current one-shot pulse ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (14) Conflicting operations If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture register, the capture trigger input takes precedence and the read data ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (16) Compare operation The capture operation may not be performed for CR0n0 set in compare mode even if a capture trigger is input. Remark (17) Changing compare register during timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (18) Edge detection <1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. (a) Immediately after a system reset high level is input to ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (23) External clock limitation <1> When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the AC characteristics. For the ...
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Function of 8-bit Timer 80 8-bit timer 80 has an 8-bit interval timer function and generates an interrupt at intervals specified in advance. Minimum Interval Time 8.0 MHz ...
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Configuration of 8-bit Timer 80 8-bit timer 80 consists of the following hardware. Table 7-2. Configuration of 8-bit Timer 80 Item Timer counter 8-bit timer counter 80 (TM80) Register 8-bit compare register 80 (CR80) Control register 8-bit timer mode ...
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This 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (TM80). It generates an interrupt request signal (INTTM80) if the two values match. CR80 is set by using ...
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Register Controlling 8-bit Timer 80 8-bit timer 80 is controlled by 8-bit timer mode control register 80 (TMC80). (1) 8-bit timer mode control register 80 (TMC80) This register is used to enable or stop the operation of 8-bit timer/counter ...
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Operation of 8-bit Timer 80 7.4.1 Operation as interval timer When 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by the count value set in advance to 8-bit compare register ...
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Figure 7-5. Timing of Interval Timer Operation t Count clock TM80 count value 00H 01H CR80 N TCE80 Count start INTTM80 Remark Interval time = ( 00H to FFH 134 CHAPTER 7 8-BIT TIMER 80 N ...
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Notes on 8-bit Timer 80 (1) Error when timer starts The time from starting the timer to generation of the match signal includes an error 1.5 clocks. This is because, if the timer is started while ...
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Functions of 8-bit Timer H1 8-bit timer H1 has the following functions. Interval timer PWM output mode Square-wave output 8.2 Configuration of 8-bit Timer H1 8-bit timer H1 consists of the following hardware. Item Timer register 8-bit timer counter ...
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H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 2 Decoder ...
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H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-2. Format of 8-bit Timer H Compare Register 01 (CMP01) ...
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Registers Controlling 8-bit Timer H1 The following three registers are used to control 8-bit timer H1. 8-bit timer H mode register 1 (TMHMD1) Port mode register 4 (PM4) Port register 4 (P4) (1) 8-bit timer H mode register 1 ...
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Figure 8-4. Format of 8-bit Timer H Mode Register 1 (TMHMD1) Address: FF70H After reset: 00H <7> Symbol TMHMD1 TMHE1 TMHE1 0 Stop timer count operation (counter is cleared Enable timer count operation (count operation started by ...
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Port mode register 4 (PM4) This register sets port 4 input/output in 1-bit units. When using the P42/TOH1 pin for timer output, clear PM42 and the output latch of P42 to 0. PM4 can be set by a 1-bit ...
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Operation of 8-bit Timer H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and 8-bit timer counter H1 is cleared to 00H. Compare ...
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Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (01H Count clock Count start 00H 01H 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 ...
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Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (2/2) Count clock Count start 00H 01H 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 Count clock Count start 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 Interval time 144 CHAPTER 8 ...
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Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during ...
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When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. At this time, ...
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Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. 00H CMP11 (M) < CMP01 (N) ...
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Figure 8-9. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) (c) Operation when CMP01 = FFH, ...
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CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 00H 01H 00H 01H 00H 8-bit timer counter H1 CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 ...
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Figure 8-9. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H Count clock 8-bit timer counter H1 00H 01H 02H CMP01 02H CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <1> The count operation ...
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Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) ...
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Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode Low-Speed Internal Oscillator Cannot Be Stopped Note 1 Watchdog timer clock Fixed source Operation after reset Operation starts with the maximum interval (2 Operation mode The ...
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Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 9-3. Configuration of Watchdog Timer Item Control registers Figure 9-1. Block Diagram of Watchdog Timer 2 Clock 16-bit input counter ...
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Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock ...
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Cautions 1. Set bits 7, 6, and and 1, respectively. Do not set the other values. 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is ...
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Operation of Watchdog Timer 9.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to low-speed internal oscillation clock. After reset is released, operation is ...
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CHAPTER 9 WATCHDOG TIMER Figure 9-4. Status Transition Diagram When “Low-Speed Internal Oscillator Cannot Be Stopped” Is Selected by Option Byte WDT clock: f Overflow time: 546.13 ms (MAX.) WDTE = “ACH” Clear WDT counter. WDT clock: f Overflow time: ...
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Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or the system clock. After ...
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Figure 9-5. Status Transition Diagram When “Low-Speed Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte WDT clock = f X Select overflow time (settable only once). WDTE = “ACH” Clear WDT counter. WDT clock ...
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Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low-speed internal oscillation ...
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When the watchdog timer operation clock is the low-speed internal oscillation clock (f instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released, operation stops for 34 s ...
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Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of the watchdog timer ...
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Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following function. ...
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Table 10-1. Sampling Time and A/D Conversion Time Reference Sampling Conversion Note 2 Note 3 Voltage Time Time Note 1 Range AV 4.5 V 12/f 36/f REF 4.0 V 24/f 72/f REF 2.85 V ...
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Figure 10-2 shows the block diagram of A/D converter. Figure 10-2. Block Diagram of A/D Converter ANI0/P20 Sample & hold circuit ANI1/P21 ANI2/P22 ANI3/P23 2 ADS1 ADS0 ADCS FR2 Analog input channel specification register (ADS) 10.2 Configuration of A/D Converter ...
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Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the D/A converter, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value ...
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Registers Used by A/D Converter The A/D converter uses the following six registers. A/D converter mode register (ADM) Analog input channel specification register (ADS) 10-bit A/D conversion result register (ADCR) 8-bit A/D conversion result register (ADCRH) Port mode control ...
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A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register ...
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Notes 2. Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 3 and 4 below are satisfied. Example When AV The sampling time is 11 more and the A/D ...
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Cautions bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0) and then A/D conversion is started, execute two NOP instructions or an instruction equivalent to two machine cycles, and set ...
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A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be read by an 8-bit memory manipulation instruction. ...
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A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Set ADCE to 1. <2> Select one channel for A/D conversion using the analog input channel specification register (ADS), and select the conversion time using FR2 to FR0. <3> ...
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Figure 10-10. Basic Operation of A/D Converter Sampling time A/D converter Sampling operation Undefined SAR ADCR, ADCRH INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. ...
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Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by ...
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A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. ...
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The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel specification ...
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How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage ...
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Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree ...
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Cautions for A/D Converter (1) Operating current in STOP mode To satisfy the DC characteristics of the supply current in the STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to ...
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ANI0/P20 to ANI3/P23 <1> The analog input pins (ANI0 to ANI3) are also used as I/O port pins (P20 to P23). When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 (P20 ...
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Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit ...
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CHAPTER 11 SERIAL INTERFACE UART6 11.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the ...
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CHAPTER 11 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed ( kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up ...
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Wakeup signal frame LIN bus RxD6 Disable Enable (input) Reception interrupt (INTSR6) <1> Edge detection (INTP0) Capture timer <1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode. <2> ...
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CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-3. Port Configuration for LIN Reception Operation P44 Output latch (P44) P30/INTP0/TI000 Output latch (P30) Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 11-11) ...
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Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware. Table 11-1. Configuration of Serial Interface UART6 Item Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift ...
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Asynchronous serial interface operation mode XP 4 register 6 (ASIM6 XCLK6 (Base clock ...
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Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register ...
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Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission status register 6 ...
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Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) Note 1 TXE6 0 Disable transmission (synchronously reset the transmission circuit). 1 Enable transmission Note 2 RXE6 0 Disable reception (synchronously reset the reception circuit). 1 Enable ...
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Cautions 2. At startup, reception enable status is entered after having set POWER6 to 1, then setting RXE6 to 1, and one clock of the base clock (f operation, set POWER6 to 0 after having set RXE6 ...
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Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, ...
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Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark CKSR6 can be refreshed (the ...
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Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Generation of reset signal sets this register to ...
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Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Generation of reset signal sets this register to 16H. ...
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Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 DIR6 0 MSB 1 LSB TXDLV6 0 Normal output of ...
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Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. By setting 1 to ISC0 and ISC1, the input source to ...
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Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. Operation stop mode Asynchronous serial interface (UART) mode 11.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be ...