UPD78F1146AF1-BA4-A Renesas Electronics America, UPD78F1146AF1-BA4-A Datasheet - Page 155

• Manufacturer Part Number: UPD78F1146AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(7) Operation speed mode control register (OSMC)
This register is used to control the step-up circuit of the flash memory for high-speed operation.
If the microcontroller operates at a low speed with a system clock of 10 MHz or less, the power consumption can
be lowered by setting this register to the default value, 00H.
OSMC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F3H
Symbol
OSMC
Cautions 1. OSMC can be written only once after reset release, by an 8-bit memory
FSEL
Figure 5-8. Format of Operation Speed Mode Control Register (OSMC)
7
0
0
1
After reset: 00H
2. Write “1” to FSEL before the following two operations.
3. The CPU waits when “1” is written to the FSEL flag.
4. To increase f
5. Flash memory can be used at a frequency of 10 MHz or lower if FSEL is 1.
Operates at a frequency of 10 MHz or less (default).
Operates at a frequency higher than 10 MHz.
manipulation instruction.
• Changing the clock prior to dividing f
• Operating the DMA controller.
Interrupt requests issued during a wait will be suspended.
The wait time is 16.6
= f
However, counting the oscillation stabilization time of f
the CPU is waiting.
or more clocks have elapsed.
IH
6
0
/2.
CHAPTER 5 CLOCK GENERATOR
R/W
CLK
User’s Manual U17854EJ9V0UD
5
0
to 10 MHz or higher, set FSEL to “1”, then change f
μ
s to 18.5
4
0
f
CLK
frequency selection
μ
s when f
3
0
CLK
CLK
to a clock other than f
= f
IH
2
0
, and 33.3
X
can continue even while
μ
1
0
s to 36.9
IH
.
FSEL
μ
CLK
s when f
0
after two
153
CLK