UPD78F1146AF1-BA4-A Renesas Electronics America, UPD78F1146AF1-BA4-A Datasheet - Page 65

• Manufacturer Part Number: UPD78F1146AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.2.1 Control registers
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
(2) Program status word (PSW)
3.2 Processor Registers
The 78K0R/KE3 products incorporate the following processor registers.
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
The program counter is a 20-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vector interrupt request acknowledgment or
PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
Reset signal generation sets PSW to 06H.
(a) Interrupt enable flag (IE)
(b) Zero flag (Z)
(c) Register bank select flags (RBS0, RBS1)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is
controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources,
and a priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
PC
19
PSW
Figure 3-13. Format of Program Status Word
IE
7
Figure 3-12. Format of Program Counter
CHAPTER 3 CPU ARCHITECTURE
Z
User’s Manual U17854EJ9V0UD
RBS1
AC
RBS0
ISP1
ISP0
CY
0
0
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