UPD78F1146AF1-BA4-A Renesas Electronics America, UPD78F1146AF1-BA4-A Datasheet - Page 502

• Manufacturer Part Number: UPD78F1146AF1-BA4-A
• Description: MCU 16BIT 78K0R/KX3 64-FBGA
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1146AF1-BA4-A

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.8 Canceling wait
resumed.
register 0 (IICC0) to 1.
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IIC0.
so that the wait state can be canceled.
IICC0, so that the wait state can be canceled.
500
The I
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)
When the above wait canceling processing is executed, the I
To cancel a wait state and transmit data (including addresses), write the data to IIC0.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IIC0 control
To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICC0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICC0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IIC0 after canceling a wait state by setting WREL0 to 1, an incorrect value may be
In addition to the above, communication is stopped if IICE0 is cleared to 0 when communication has been aborted,
If the I
Note Master only
2
C usually cancels a wait state by the following processing.
2
C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
Note
Note
2
C cancels the wait state and communication is