ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 72

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

(1)
Figure 46. Sampling Received Data
“Double-speed
Note:
1. This figure is not valid when the UART speed is doubled. See
Transmission” on page 78
for a detailed description.
When the stop bit enters the Receiver, the majority of the three samples must be one to
accept the stop bit. If two or more samples are logical “0”s, the Framing Error (FEn) Flag
in the UART Control and Status Register (UCSRnA) is set. Before reading the UDRn
Register, the user should always check the FEn bit to detect framing errors.
Whether or not a valid stop bit is detected at the end of a character reception cycle, the
data is transferred to UDRn and the RXCn Flag in UCSRnA is set. UDRn is in fact two
physically separate registers, one for transmitted data and one for received data. When
UDRn is read, the Receive Data Register is accessed, and when UDRn is written, the
Transmit Data Register is accessed. If 9-bit data word is selected (the CHR9n bit in the
UART Control and Status Register [UCSRnB] is set), the RXB8n bit in UCSRnB is
loaded with bit 9 in the Transmit Shift Register when data is transferred to UDRn.
If, after having received a character, the UDRn Register has not been read since the last
receive, the OverRun (ORn) Flag in UCSRnB is set. This means that the last data byte
shifted into the Shift Register could not be transferred to UDRn and has been lost. The
ORn bit is buffered and is updated when the valid data byte in UDRn is read. Thus, the
user should always check the ORn bit after reading the UDRn Register in order to detect
any overruns if the baud rate is high or CPU load is high.
When the RXEN bit in the UCSRnB Register is cleared (zero), the Receiver is disabled.
This means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the
UART Receiver will be connected to PD0 (UART0) or PB2 (UART1), which is forced to
be an input pin regardless of the setting of the DDD0 in DDRD (UART0) or DDB2 bit in
DDRB (UART1). When PD0 (UART0) or PB2 (UART1) is forced to input by the UART,
the PORTD0 (UART0) or PORTB2 (UART1) bit can still be used to control the pull-up
resistor on the pin.
Note that PB2 (UART1) also is used as one of the input pins to the Analog Comparator.
It is therefore not recommended to use UART1 if the Analog Comparator also is used in
the application at the same time.
When the CHR9n bit in the UCSRnB Register is set, transmitted and received charac-
ters are nine bits long plus start and stop bits. The ninth data bit to be transmitted is the
TXB8n bit in UCSRnB Register. This bit must be set to the wanted value before a trans-
mission is initiated by writing to the UDRn Register. The ninth data bit received is the
RXB8n bit in the UCSRnB Register.
ATmega161(L)
72
1228D–AVR–02/07