ATMEGA48V-10AI Atmel, ATMEGA48V-10AI Datasheet - Page 211

• Manufacturer Part Number: ATMEGA48V-10AI
• Description: IC AVR MCU 4K 5V 10MHZ 32-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA48V-10AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA48V-12AI; ATMEGA48V-12AI

21.3.4
21.3.5
2545S–AVR–07/10
Data Packet Format
Combining Address and Data Packets into a Transmission
Figure 21-4. Address Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 21-5. Data Packet Format
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 21-6
between the SLA+R/W and the STOP condition, depending on the software protocol imple-
mented by the application software.
Transmitter
Aggregate
SDA from
SDA from
SCL from
Receiver
SDA
Master
SCL
SDA
SLA+R/W
shows a typical data transmission. Note that several data bytes can be transmitted
START
Data MSB
Addr MSB
1
1
2
2
Data Byte
7
Addr LSB
Data LSB
8
7
ATmega48/88/168
ACK
9
R/W
8
ACK
STOP, REPEATED
9
START or Next
Data Byte
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