ATMEGA48V-10AI Atmel, ATMEGA48V-10AI Datasheet - Page 80

• Manufacturer Part Number: ATMEGA48V-10AI
• Description: IC AVR MCU 4K 5V 10MHZ 32-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA48V-10AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA48V-12AI; ATMEGA48V-12AI

13.3.2
80
ATmega48/88/168
Alternate Functions of Port C
Notes:
Table 13-5.
The Port C pins with alternate functions are shown in
Table 13-6.
The alternate pin configuration is as follows:
• RESET/PCINT14 – Port C, Bit 6
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Port Pin
PC6
PC5
PC4
PC3
PC2
PC1
PC0
1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses),
EXTCK means that external clock is selected (by the CKSEL fuses).
PB3/MOSI/
OC2/PCINT3
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPE • MSTR +
OC2A ENABLE
SPI MSTR OUTPUT
+ OC2A
PCINT3 • PCIE0
1
PCINT3 INPUT
SPI SLAVE INPUT
–
Overriding Signals for Alternate Functions in PB3..PB0
Port C Pins Alternate Functions
Alternate Function
RESET (Reset pin)
PCINT14 (Pin Change Interrupt 14)
ADC5 (ADC Input Channel 5)
SCL (2-wire Serial Bus Clock Line)
PCINT13 (Pin Change Interrupt 13)
ADC4 (ADC Input Channel 4)
SDA (2-wire Serial Bus Data Input/Output Line)
PCINT12 (Pin Change Interrupt 12)
ADC3 (ADC Input Channel 3)
PCINT11 (Pin Change Interrupt 11)
ADC2 (ADC Input Channel 2)
PCINT10 (Pin Change Interrupt 10)
ADC1 (ADC Input Channel 1)
PCINT9 (Pin Change Interrupt 9)
ADC0 (ADC Input Channel 0)
PCINT8 (Pin Change Interrupt 8)
PB2/SS/
OC1B/PCINT2
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
OC1B ENABLE
OC1B
PCINT2 • PCIE0
1
PCINT2 INPUT
SPI SS
–
Table
PB1/OC1A/
PCINT1
0
0
0
0
OC1A ENABLE
OC1A
PCINT1 • PCIE0
1
PCINT1 INPUT
–
13-6.
PB0/ICP1/
PCINT0
0
0
0
0
0
0
PCINT0 • PCIE0
1
PCINT0 INPUT
ICP1 INPUT
–
2545S–AVR–07/10