AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 126

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

16.8.0.2
16.8.0.3
126
AT8xC51SND1C
Table 115. MMCON2 Register
MMCON2 (S:E6h) – MMC Control Register 2
Reset Value = 0000 0000b
Table 116. MMSTA Register
MMSTA (S:DEh Read Only) – MMC Control and Status Register
MMCEN
Number
Number
7 - 6
4-3
2-1
Bit
Bit
7
7
6
5
0
7
5
-
Mnemonic Description
Mnemonic Description
DATD1:0
MMCEN
FLOWC
CBUSY
DCR
DCR
CCR
Bit
Bit
6
6
-
-
-
MMC Clock Enable Bit
Set to enable the MCLK clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
Data Controller Reset Bit
Set and clear to reset the data line controller in case of transfer abort.
Command Controller Reset Bit
Set and clear to reset the command line controller in case of transfer abort.
Reserved
The value read from these bits is always 0. Do not set these bits.
Used to delay the data transmission after a response from 3 MMC clock periods
(all bits cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock
periods.
MMC Flow Control Bit
Set to enable the flow control during data transfers.
Clear to disable the flow control during data transfers.
Reserved
The value read from these bits is always 0. Do not set these bits.
Card Busy Flag
Set by hardware when the card sends a busy state on the data line.
Cleared by hardware when the card no more sends a busy state on the data line.
Data Transmission Delay Bits
CBUSY
CCR
5
5
CRC16S
4
4
-
DATFS
3
3
-
CRC7S
DATD1
2
2
RESPFS
DATD0
1
1
4109L–8051–02/08
FLOWC
CFLCK
0
0