AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 175

IC MCU FLASH MP3 DECODER 80-TQFP

AT80C51SND1C-ROTIL

Manufacturer Part Number
AT80C51SND1C-ROTIL
Description
IC MCU FLASH MP3 DECODER 80-TQFP
Manufacturer
Atmel
Series
80Cr
Datasheet

Specifications of AT80C51SND1C-ROTIL

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
Peripherals
Audio, I²S, MP3, PCM, POR, WDT
Number Of I /o
44
Program Memory Type
ROMless
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
AT80C51SND1CROTIL

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT80C51SND1C-ROTIL
Manufacturer:
Atmel
Quantity:
10 000
21.1.1
21.1.2
21.1.3
4109L–8051–02/08
Clock Generator
Channel Selection
Conversion Precision
Figure 21-2. Timing Diagram
The ADC clock is generated by division of the peripheral clock (see details in section “X2 Fea-
ture”, page 13). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure 21-
3 shows the ADC clock generator and its calculation formula
Figure 21-3. ADC Clock Generator and Symbol Caution:
Note:
The channel on which conversion is performed is selected by the ADCS bit in ADCON register
according to Table 147.
Table 147. ADC Channel Selection
The 10-bit precision conversion is achieved by stopping the CPU core activity during conversion
for limiting the digital noise induced by the core. This mode called the Pseudo-Idle mode
enabled by setting the ADIDL bit in ADCON register
Section "Conversion Launching", page 176), the CPU core is stopped until the end of the con-
1. In all cases, the ADC clock frequency may be higher than the maximum F
2. The ADCD value of 0 is equivalent to an ADCD value of 32.
ADEOC
ADSST
CLOCK
ADEN
reported in the section “Analog to Digital Converter”, page 199.
PER
CLK
T
÷ 2
SETUP
ADCS
0
1
T
ADCD4:0
ADCLK
ADCLK
ADCclk
=
(3)
-------------------------
2 ADCD
PERclk
. Thus, when conversion is launched (see
T
ADC Clock
CONV
(1)
.
AT8xC51SND1C
Channel
AIN1
AIN0
ADC Clock Symbol
CLOCK
ADCLK
ADC
parameter
(1),(2)
175
is

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