AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 54

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

Figure 11-1. Timer 0 and Timer 1 Clock Controller and Symbols
11.3
11.3.1
Figure 11-2. Timer/Counter x (x = 0 or 1) in Mode 0
54
Timer 0
AT8xC51SND1C
Mode 0 (13-bit Timer)
CLOCK
INTx
CLOCK
CLOCK
TIMx
OSC
Tx
PER
TMOD Reg
Timer 0 Clock Symbol
GATEx
CLOCK
÷ 6
TIM0
÷
2
Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 11-2
through Figure 11-8 show the logical configuration of each mode.
Timer 0 is controlled by the four lower bits of TMOD register (see Table 62) and bits 0, 1, 4 and
5 of TCON register (see Table 61). TMOD register selects the method of Timer gating (GATE0),
Timer or Counter operation (C/T0#) and mode of operation (M10 and M00). TCON register pro-
vides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and
interrupt type control bit (IT0).
For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the
selected input. Setting GATE0 and TR0 allows external pin INT0 to control Timer operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt
request.
It is important to stop Timer/Counter before changing mode.
Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with
a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 11-2).
The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow
increments TH0 register. Figure 11-3 gives the overflow period calculation formula.
TMOD Reg
C/Tx#
CKCON.1
TCON Reg
T0X2
0
1
0
1
TRx
Timer 0 Clock
(5 Bits)
TLx
CLOCK
CLOCK
OSC
PER
Timer 1 Clock Symbol
(8 Bits)
THx
CLOCK
TIM1
÷
2
Overflow
CKCON.2
T1X2
0
1
TCON reg
TFx
Timer 1 Clock
Timer x
Interrupt
Request
4109L–8051–02/08