LPC2104BBD48,151 NXP Semiconductors, LPC2104BBD48,151 Datasheet - Page 18

• Manufacturer Part Number: LPC2104BBD48,151
• Description: IC ARM7 MCU FLASH 128K 48-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2100r

Specifications of LPC2104BBD48,151

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-LQFP
• For Use With: 568-1756 - BOARD EVAL FOR LPC210X ARM MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 568-1220; 935273746151; LPC2104BBD48-S

NXP Semiconductors
LPC2104_2105_2106_7
Product data sheet
6.12.1 Features
6.12.2 Features available in LPC2104/2105/2106/01 only
6.13.1 Features
6.12 SPI serial I/O controller
6.13 SSP controller (LPC2104/2015/2106/01 only)
6.14 General purpose timers
The SPI is a full duplex serial interface, designed to be able to handle multiple masters
and slaves connected to a given bus. Only a single master and a single slave can
communicate on the interface during a given data transfer. During a data transfer the
master always sends a byte of data to the slave, and the slave always sends a byte of data
to the master.
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of four to 16 bits of data flowing from the master to the
slave and from the slave to the master.
Because the SSP and SPI peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Application can switch on the
fly from SPI to SSP and back.
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. It also includes up to four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt.
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Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, serial, full duplex communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
Selectable transfer width of eight to 16 bit per frame.
When the SPI interface is used in Master mode, the SSEL pin is not needed (can be
used for a different function).
Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four to 16 bits per frame.
Rev. 07 — 20 June 2008
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
© NXP B.V. 2008. All rights reserved.
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