Z8F6422AR020SC Zilog, Z8F6422AR020SC Datasheet - Page 245

IC ENCORE MCU FLASH 64K 64LQFP

Z8F6422AR020SC

Manufacturer Part Number
Z8F6422AR020SC
Description
IC ENCORE MCU FLASH 64K 64LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheets

Specifications of Z8F6422AR020SC

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
Z8F642x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
269-4678 - KIT DEV FOR Z8F642 MCU 44 PIN269-4677 - KIT DEV FOR Z8F642 MCU 28PIN269-4540 - KIT DEV FOR Z8 ENCORE 16K TO 64K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3302

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F6422AR020SC
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8F6422AR020SC00TR
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8F6422AR020SC2104
Manufacturer:
Zilog
Quantity:
10 000
PS019921-0308
(Output)
(Input)
MOSI
MISO
SCK
SPI Master Mode Timing
Figure 52
shown with SCK rising edge used to source MOSI output data, SCK falling edge used to
sample MISO input data. Timing on the SS output pin(s) is controlled by software.
Table 117. SPI Master Mode Timing
Parameter
SPI Master
T
T
T
1
2
3
T1
and
Abbreviation
SCK Rise to MOSI output Valid Delay
MISO input to SCK (receive edge) Setup Time
MISO input to SCK (receive edge) Hold Time
Table 117
Figure 52. SPI Master Mode Timing
provide timing information for SPI Master mode pins. Timing is
T2
Input Data
T3
Output Data
Z8 Encore! XP
Product Specification
Electrical Characteristics
Min
®
20
-5
0
Delay (ns)
F64XX Series
Max
+5
231

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