Z8F6422AR020SC Zilog, Z8F6422AR020SC Datasheet - Page 89

• Manufacturer Part Number: Z8F6422AR020SC
• Description: IC ENCORE MCU FLASH 64K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F6422AR020SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z8F642x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 269-4678 - KIT DEV FOR Z8F642 MCU 44 PIN269-4677 - KIT DEV FOR Z8F642 MCU 28PIN269-4540 - KIT DEV FOR Z8 ENCORE 16K TO 64K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3302

Table 38. Interrupt Control Register (IRQCTL)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
Interrupt Control Register
IRQE
R/W
7
PADxS—PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
where x indicates the specific GPIO Port pin number (0 through 7).
The Interrupt Control (IRQCTL) register
interrupts.
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI or IRET instruction, or by a direct register write of
a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of
an interrupt request, or Reset.
0 = Interrupts are disabled
1 = Interrupts are enabled
Reserved—Must be 0.
6
5
4
FCFH
(Table
0
Reserved
R
3
38) contains the master enable bit for all
Z8 Encore! XP
2
Product Specification
1
®
Interrupt Controller
F64XX Series
0
75