ZGP323LAH2808G Zilog, ZGP323LAH2808G Datasheet - Page 49

IC Z8 GP MCU 8K OTP 28SSOP

ZGP323LAH2808G

Manufacturer Part Number
ZGP323LAH2808G
Description
IC Z8 GP MCU 8K OTP 28SSOP
Manufacturer
Zilog
Series
Z8® GP™r
Datasheets

Specifications of ZGP323LAH2808G

Core Processor
Z8
Core Size
8-Bit
Speed
8MHz
Peripherals
HLVD, POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
237 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
269-4409
ZGP323LAH2808G
PS023709-0208
Table 11. Interrupt Types, Sources, and Vectors
When more than one interrupt is pending, priorities are resolved by a programmable
priority encoder controlled by the Interrupt Priority register. An interrupt machine cycle
activates when an interrupt request is granted. As a result, all subsequent interrupts are
disabled, and the Program Counter and Status Flags are saved. The cycle then branches to
the Program Memory vector location reserved for that interrupt. All ZGP323L interrupts
are vectored through locations in the Program Memory. This memory location and the
next byte contain the 16-bit address of the interrupt service routine for that particular
interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked,
and the Interrupt Request register is polled to determine which of the interrupt requests
require service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge
triggered. These interrupts are user-programmable. The software can poll to identify the
state of the pin.
Programming bits for the Interrupt Edge Select are located in the IRQ register (R250), bits
D7 and D6. The configuration is indicated in
Table 12. IRQ Register
Name
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
D7
0
0
1
1
Note: F = Falling Edge; R = Rising Edge
IRQ
D6
0
1
0
1
Source
P32
P33
P31, T
T16
T8
LVD
IRQ2 (P31)
F
F
R
R/F
IN
Interrupt Edge
Vector Location
0,1
2,3
4,5
6,7
8,9
10,11
IRQ0 (P32)
F
R
F
R/F
Comments
External (P32), Rising, Falling Edge Triggered
External (P33), Falling Edge Triggered
External (P31), Rising, Falling Edge Triggered
Internal
Internal
Internal
Table
12.
Product Specification
Functional Description
ZGP323L
45

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