ZGP323LAH2808G Zilog, ZGP323LAH2808G Datasheet - Page 51

• Manufacturer Part Number: ZGP323LAH2808G
• Description: IC Z8 GP MCU 8K OTP 28SSOP
• Manufacturer: Zilog
• Series: Z8® GP™r

Specifications of ZGP323LAH2808G

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: HLVD, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4409; ZGP323LAH2808G

PS023709-0208
immediately after it wakes up from STOP mode. The Stop Mode Recovery delay must be
selected (bit 5 of SMR = 1) if resonator or crystal is used as clock source.
For resonator and crystal oscillation, the oscillation ground must go directly to the ground
pin of the microcontroller. It should use the shortest distant and isolate from other
connection.
Power-On Reset
A timer circuit clocked by a dedicated on-board RC-oscillator is used for the Power-On
Reset timer function. The POR time allows V
before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
•
•
The POR timer is 2.5 ms minimum. Bit 5 of the Stop Mode register determines whether
the POR timer is bypassed after Stop Mode Recovery (typical for external clock).
HALT Mode
This instruction turns OFF the internal CPU clock, but not the XTAL oscillation. The
counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain
active. The devices are recovered by interrupts, either externally or internally generated.
An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt
service routine, the program continues from the instruction after HALT mode.
STOP Mode
This instruction turns OFF the internal clock and external crystal oscillation, reducing the
standby current to 10 µA or less. STOP mode is terminated only by a reset, such as WDT
timeout, POR, SMR or external reset. This condition causes the processor to restart the
application program at address
instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP
(Opcode =
or
Power Fail to Power OK status, including Waking up from V
Stop Mode Recovery (if D5 of SMR = 1)
WDT Timeout
FF
6F
FF
7F
FFH
) immediately before the appropriate sleep instruction, as follows:
NOP
Stop
NOP
HALT
000CH
; clear the pipeline
; enter Stop Mode
; clear the pipeline
; enter HALT Mode
. To enter STOP (or HALT) mode, first flush the
DD
and the oscillator circuit to stabilize
Product Specification
BO
Standby
Functional Description
ZGP323L
47