ST7FMC2S4TCE STMicroelectronics, ST7FMC2S4TCE Datasheet - Page 73

• Manufacturer Part Number: ST7FMC2S4TCE
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC2S4TCE

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-LQFP
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-6408 - BOARD EVAL BLDC SENSORLESS MOTOR497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ON-CHIP PERIPHERALS (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:4 = OE[3:0] PWM Output Enable
These bits are set and cleared by software. They
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
Note: When an OPx bit is modified, the PWMx out-
put signal polarity is immediately reversed.
OE3
Counter <= OCRx
7
OE2
1
0
PWMx output level
OE1
OE0
Counter > OCRx
OP3
0
1
OP2
OP1
OPx
OP0
0
1
0
DUTY CYCLE REGISTERS (PWMDCRx)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx
register of each PWM channel to determine the
second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR regis-
ters allow the duty cycle to be set independently
for each PWM channel.
DC7
7
DC6
DC5
DC4
ST7MC1xx/ST7MC2xx
DC3
DC2
DC1
73/309
DC0
0
1