MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 146

no-image

MC68HC908AB32CFU

Manufacturer Part Number
MC68HC908AB32CFU
Description
IC MCU 8MHZ 32K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908AB32CFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908AB32CFU
Manufacturer:
MOTOROLA
Quantity:
1 372
Part Number:
MC68HC908AB32CFU
Manufacturer:
MC
Quantity:
852
Part Number:
MC68HC908AB32CFU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC908AB32CFU
Manufacturer:
MOT
Quantity:
39
Part Number:
MC68HC908AB32CFU
Manufacturer:
FRE/MOT
Quantity:
20 000
Part Number:
MC68HC908AB32CFUE
Manufacturer:
ATMEL
Quantity:
1 001
Part Number:
MC68HC908AB32CFUE
Manufacturer:
FREE
Quantity:
6
Clock Generator Module (CGM)
9.6.2 PLL Bandwidth Control Register (PBWC)
Technical Data
146
NOTE:
Address:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See
Bits [3:0] — Unimplemented bits
The PLL bandwidth control register does the following:
Reset:
Read:
Write:
the other. During the transition, CGMOUT is held in stasis. See
Base Clock Selector
the BCS bit.
These bits provide no function and always read as 1.
1 = CGMOUT driven by CGMVCLK/2
0 = CGMOUT driven by CGMXCLK/2
Selects automatic or manual (software-controlled) bandwidth
control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking
mode.
Figure 9-7. PLL Bandwidth Control Register (PBWC)
$001D
AUTO
Bit 7
0
Clock Generator Module (CGM)
9.4.3 Base Clock Selector
= Unimplemented
LOCK
6
0
ACQ
Circuit. Reset and the STOP instruction clear
5
0
XLD
4
0
Circuit.
3
0
0
MC68HC908AB32
Freescale Semiconductor
2
0
0
1
0
0
Rev. 1.1
Bit 0
9.4.3
0
0

Related parts for MC68HC908AB32CFU