MC68HC711E20CFN3

Manufacturer Part NumberMC68HC711E20CFN3
DescriptionIC MCU 3MHZ 20K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E20CFN3 datasheets
 


Specifications of MC68HC711E20CFN3

Core ProcessorHC11Core Size8-Bit
Speed3MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size20KB (20K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size768 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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M68HC11E Family
Data Sheet
HC11
Microcontrollers
M68HC11E
Rev. 5.1
07/2005
freescale.com

MC68HC711E20CFN3 Summary of contents

  • Page 1

    M68HC11E Family Data Sheet HC11 Microcontrollers M68HC11E Rev. 5.1 07/2005 freescale.com ...

  • Page 2

    ...

  • Page 3

    ... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. ...

  • Page 4

    ... MC68HC711E9 device only. July, 2005 5.1 Updated to meet Freescale identity guidelines. 4 Revision History Description M68HC11E Family Data Sheet, Rev. 5.1 Page Number(s) 44 175 175 110 153 154 157 163 167 169 172 175 181 Throughout 23 100 175 Throughout Freescale Semiconductor ...

  • Page 5

    ... EB184 — Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 EB188 — Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 EB296 — Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 5 ...

  • Page 6

    ... List of Chapters 6 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 7

    ... System Configuration Register 2.3.3.2 RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.3.3.3 System Configuration Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.4 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.4.1 Programming an Individual EPROM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.4.2 Programming the EPROM with Downloaded Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Freescale Semiconductor Chapter 1 General Description ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PPE ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STBY Chapter 2 M68HC11E Family Data Sheet, Rev. 5.1 7 ...

  • Page 8

    ... Condition Code Register (CCR 4.2.6.1 Carry/Borrow ( 4.2.6.2 Overflow ( 4.2.6.3 Zero (Z 4.2.6.4 Negative ( 4.2.6.5 Interrupt Mask ( 4.2.6.6 Half Carry ( 4.2.6.7 X Interrupt Mask ( 4.2.6.8 STOP Disable ( Chapter 3 Analog-to-Digital (A/D) Converter Chapter 4 Central Processor Unit (CPU) M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 9

    ... Non-Maskable Interrupt Request (XIRQ 5.5.3 Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.5.4 Software Interrupt (SWI 5.5.5 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.5.6 Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.6 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Freescale Semiconductor Chapter 5 Resets and Interrupts M68HC11E Family Data Sheet, Rev. 5.1 9 ...

  • Page 10

    ... SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.7.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.7.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.7.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10 Chapter 6 Parallel Input/Output (I/O) Ports Chapter 7 Chapter 8 Serial Peripheral Interface (SPI) M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 11

    ... MC68L11E9/E20 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.11 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.12 MC68L11E9/E20 Peripheral Port Timing 163 10.13 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.14 MC68L11E9/E20 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 167 Freescale Semiconductor Chapter 9 Timing Systems Chapter 10 Electrical Characteristics M68HC11E Family Data Sheet, Rev. 5.1 ...

  • Page 12

    ... M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 EB188 — Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 EB296 — Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 12 Chapter 11 Appendix A Development Support Appendix B EVBU Schematic M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 13

    ... Three input capture (IC) channels – Four output compare (OC) channels – One additional channel, selectable as fourth IC or fifth OC • 8-bit pulse accumulator • Real-time interrupt circuit Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 13 ...

  • Page 14

    ... Most pins on these MCUs serve two or more functions, as described in the following paragraphs. Refer to Figure 1-2, Figure 1-3, Figure assignments for the PLCC/CLCC, QFP, TQFP, SDIP, and DIP packages. 14 1-1. 1-4, Figure 1-5, and Figure 1-6 M68HC11E Family Data Sheet, Rev. 5.1 which show the M68HC11 E-series pin Freescale Semiconductor ...

  • Page 15

    ... MODE CONTROL CLOCK LOGIC TIMER SYSTEM BUS EXPANSION ADDRESS PORT A PORT applies only to devices with EPROM/OTPROM. PPE Figure 1-1. M68HC11 E-Series Block Diagram Freescale Semiconductor IRQ XIRQ/V RESET PPE* INTERRUPT LOGIC M68HC11 CPU ADDRESS/DATA PERIPHERAL STROBE AND HANDSHAKE PARALLEL I/O CONTROL ...

  • Page 16

    ... EPROM/OTPROM. PPE Figure 1-2. Pin Assignments for 52-Pin PLCC and CLCC M68HC11 E SERIES PPE 19 IRQ 20 M68HC11E Family Data Sheet, Rev. 5.1 46 PE5/AN5 PE1/AN1 45 44 PE4/AN4 43 PE0/AN0 42 PB0/ADDR8 PB1/ADDR9 41 40 PB2/ADDR10 PB3/ADDR11 39 PB4/ADDR12 38 37 PB5/ADDR13 36 PB6/ADDR14 PB7/ADDR15 35 34 PA0/IC3 Freescale Semiconductor ...

  • Page 17

    ... PA0/IC3 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PE0/AN0 PE4/AN4 PE1/AN1 PE5/AN5 1. V applies only to devices with EPROM/OTPROM. PPE Figure 1-3. Pin Assignments for 64-Pin QFP Freescale Semiconductor M68HC11 E SERIES M68HC11E Family Data Sheet, Rev. 5.1 Pin Descriptions PD0/RxD IRQ ...

  • Page 18

    ... PE4/AN4 PE1/AN1 PE5/AN5 1. V applies only to devices with EPROM/OTPROM. PPE Figure 1-4. Pin Assignments for 52-Pin TQFP M68HC11 E SERIES M68HC11E Family Data Sheet, Rev. 5.1 PD0/RxD IRQ (1) XIRQ/V PPE RESET PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 PC0/ADDR0/DATA0 XTAL Freescale Semiconductor ...

  • Page 19

    ... PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 * V Figure 1-5. Pin Assignments for 56-Pin SDIP Freescale Semiconductor MODB/V STBY 2 MODA/LIR 3 STRA/ STRB/R/W 6 EXTAL 7 XTAL M68HC11 E SERIES 15 16 RESET 17 * XIRQ/V PPE 18 IRQ 19 PD0/RxD PD1/TxD 22 PD2/MISO 23 PD3/MOSI 24 PD4/SCK 25 PD5/ applies only to devices with EPROM/OTPROM. ...

  • Page 20

    ... PB1/ADDR9 34 15 PB0/ADDR8 16 33 PE0/AN0 32 17 PE1/AN1 31 18 PE2/AN2 19 30 PE3/AN3 STBY M68HC11E Family Data Sheet, Rev. 5 PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD PD0/RxD IRQ XIRQ RESET PC7/ADDR7/DATA7 PC6/ADDR6/DATA6 PC5/ADDR5/DATA5 PC4/ADDR4/DATA4 PC3/ADDR3/DATA3 PC2/ADDR2/DATA2 PC1/ADDR1/DATA1 PC0/ADDR0/DATA0 XTAL EXTAL STRB/R/W E STRA/AS MODA/LIR Freescale Semiconductor ...

  • Page 21

    ... MCU as possible. Bypass requirements vary, depending on how heavily the MCU pins are loaded. MANUAL RESET SWITCH 4.7 kΩ OPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCH Figure 1-8. External Reset Circuit with Delay Freescale Semiconductor and the power supply ...

  • Page 22

    ... Figure 1-7 and Figure 1-8. CAUTION for further information. CAUTION M68HC11E Family Data Sheet, Rev. 5.1 falls below the minimum DD Figure 1-9 and Freescale Semiconductor ...

  • Page 23

    ... Because the XIRQ input is level-sensitive, it can be connected to a multiple-source wired-OR network with an external pullup resistor to V Whenever XIRQ or IRQ is used with multiple interrupt sources each source must drive the interrupt input with an open-drain type of driver to avoid contention between outputs. Freescale Semiconductor 10 MΩ CRYSTAL ...

  • Page 24

    ... V should be at least 3 Vdc greater than V RH • V and V should be between NOTE Interrupts. CAUTION ) STBY Memory and M68HC11E Family Data Sheet, Rev. 5.1 pin PPE voltage, the internal RAM and part DD input. This allows RAM contents removed and DD Freescale Semiconductor ...

  • Page 25

    ... PA7 can function as general-purpose I timer output compare for OC1. PA7 is also the input to the pulse accumulator, even while functioning as a general-purpose I OC1 output. Freescale Semiconductor for further information. for more information about IRVNE (internal read M68HC11E Family Data Sheet, Rev. 5.1 ...

  • Page 26

    ... PD4/SCK PD5/SS STRA STRB PE0/AN0 PE1/AN1 PE3/AN2 PE3/AN3 PE4/AN4 PE5/AN5 PE6/AN6 PE7/AN7 M68HC11E Family Data Sheet, Rev. 5.1 Expanded and Test Modes ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR0/DATA0 ADDR1/DATA1 ADDR2/DATA2 ADDR3/DATA3 ADDR4/DATA4 ADDR5/DATA5 ADDR6/DATA6 ADDR7/DATA7 AS R/W Freescale Semiconductor ...

  • Page 27

    ... It is customary to have an external pullup resistor on lines that are driven by open-drain devices. Port C can only be configured for wired-OR operation when the MCU is in single-chip mode. Refer to Parallel Input/Output (I/O) Ports Freescale Semiconductor Ports. for additional information about port C functions. M68HC11E Family Data Sheet, Rev. 5.1 ...

  • Page 28

    ... PD5 is the slave select (SS) input. 1.4.16 Port E Use port E for general-purpose or analog-to-digital (A/D) inputs. If high accuracy is required for A/D conversions, avoid reading port E during sampling, as small disturbances can reduce the accuracy of that result. 28 CAUTION M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 29

    ... active-high latch enable signal for an external address latch. Address information is allowed through the transparent latch while AS is high and is latched when AS drives low. Freescale Semiconductor NOTE M68HC11E Family Data Sheet, Rev. 5.1 ...

  • Page 30

    ... ROM becomes present in the memory map. Reset and interrupt vectors are 30 NOTE HC373 M68HC11E Family Data Sheet, Rev. 5.1 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 WE OE DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Freescale Semiconductor ...

  • Page 31

    ... MCU register and control bit assignments. Reset states shown are for single-chip mode only. $0000 EXT $1000 $B600 EXT $D000 $FFFF EXPANDED BOOTSTRAP Figure 2-2. Memory Map for MC68HC11E0 Freescale Semiconductor 2-3, Figure 2-4, Figure 2-5, and Figure 2-4, Figure 2-5, and Figure 0000 ...

  • Page 32

    ... NORMAL MODES INTERRUPT VECTORS 0000 512 BYTES RAM 01FF 1000 64-BYTE REGISTER BLOCK 103F B600 512 BYTES EEPROM B7FF BOOT BFC0 BF00 SPECIAL MODES ROM INTERRUPT VECTORS BFFF BFFF 12 KBYTES ROM/EPROM D000 NORMAL FFC0 MODES INTERRUPT FFFF FFFF VECTORS Freescale Semiconductor ...

  • Page 33

    ... Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each. Figure 2-5. Memory Map for MC68HC(7)11E20 $0000 EXT $1000 EXT $F800 $FFFF SINGLE EXPANDED CHIP Figure 2-6. Memory Map for MC68HC811E2 Freescale Semiconductor EXT EXT EXT EXT BOOTSTRAP SPECIAL TEST EXT EXT BOOTSTRAP SPECIAL TEST M68HC11E Family Data Sheet, Rev ...

  • Page 34

    ... PB2 PB1 PCL4 PCL3 PCL2 PCL1 DDRC4 DDRC3 DDRC2 DDRC1 PD4 PD3 PD2 PD1 DDRD4 DDRD3 DDRD2 DDRD1 PE4 PE3 PE2 PE1 FOC4 FOC5 OC1M4 OC1M3 Reserved U = Unaffected Freescale Semiconductor Bit 0 PA0 I R INVB 1 PC0 PB0 0 PCL0 R DDRC0 0 PD0 I DDRD0 0 PE0 0 0 ...

  • Page 35

    ... High (TOC1H) See page 134. Timer Output Compare 1 Register $1017 Low (TOC1L) See page 134. Timer Output Compare 2 Register $1018 High (TOC2H) See page 134. Figure 2-7. Register and Control Bit Assignments (Sheet Freescale Semiconductor Bit Read: OC1D7 OC1D6 OC1D5 Write: Reset: 0 ...

  • Page 36

    ... OM4 OL4 OM5 EDG1A EDG2B EDG2A EDG3B OC4I I4/O5I IC1I IC2I OC4F I4/O5F IC1F IC2F PAII PR1 Reserved U = Unaffected Freescale Semiconductor Bit 0 Bit 0 1 Bit 8 1 Bit 0 1 Bit 8 1 Bit 0 1 Bit 8 1 Bit 0 1 OL5 0 EDG3A 0 IC3I 0 IC3F 0 PR0 0 ...

  • Page 37

    ... SCP2 adds ÷39 to SCI prescaler and is present only in MC68HC(7)11E20. Serial Communications Data Reg- $102F ister (SCDR) See page 110. Analog-to-Digital Control Status $1030 Register (ADCTL) See page 62. Figure 2-7. Register and Control Bit Assignments (Sheet Freescale Semiconductor Bit Read: TOF RTIF PAOVF Write: Reset: ...

  • Page 38

    ... BPRT2 BPRT1 EXCOL EXROW (1) (1) DLY CME CR1 Bit 4 Bit 3 Bit 2 Bit BYTE ROW ERASE EELAT IRV(NE) PSEL3 PSEL2 PSEL1 RAM0 REG3 REG2 REG1 Reserved U = Unaffected Freescale Semiconductor Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 BPRT0 1 PGM (1) CR0 0 Bit 0 0 EPGM 0 PSEL0 0 REG0 1 ...

  • Page 39

    ... Adjustments to the circuit must be made for devices that operate at lower voltages. Using the MODB/V pin may require external hardware, but can be justified when a significant amount STBY of external circuitry is operating from V be held low whenever V Interrupts. Freescale Semiconductor Bit Read: ...

  • Page 40

    ... Table 2-1, which is a summary of mode pin operation, the mode control bits, and the four operating modes MAX 690 OUT V BATT + STBY . DD M68HC11E Family Data Sheet, Rev. 5.1 TO MODB/V STBY OF M68HC11 Connections 2.3.3.1 System Configuration Register ), which STBY Freescale Semiconductor ...

  • Page 41

    ... The initial value of MDA equals the logic level present on the MODA pin at the rising edge of reset. These two bits can be read at any time. They can be written anytime in special modes. MDA can be written only once in normal modes. SMOD cannot be set once it has been cleared. Input MODB 1 1 Freescale Semiconductor Mode RBOOT 0 Single chip 0 1 ...

  • Page 42

    ... Anytime Bits [7:2] Set bits only Bits [7:6], bit 3 See HPRIO description — — All, set or clear — All, set or clear — All, set or clear See HPRIO description — All, set or clear Freescale Semiconductor IRVNE Can Be Written Once Once Once Once ...

  • Page 43

    ... U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register. Figure 2-10. System Configuration Register (CONFIG) Freescale Semiconductor Programming MC68HC711E9 Devices with PCbug11 and NOTE 2-11 ...

  • Page 44

    ... M68HC11E Family Data Sheet, Rev. 5 Bit 0 NOCOP EEON U( U( Freescale Semiconductor ...

  • Page 45

    ... REG[3:0] — 64-Byte Register Block Position These four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal registers. The register block, positioned at the beginning of any 4-Kbyte page in the memory map, is initialized to address $1000 out of reset. Refer to Freescale Semiconductor Interrupts ...

  • Page 46

    ... Bit 0 (1) (1) CR1 CR0 2.5.1 EEPROM and Chapter 3 Freescale Semiconductor ...

  • Page 47

    ... EPROM/OTPROM programming called the EPROG register. As described in the following subsections, these two methods of programming and verifying EPROM are possible: 1. Programming an individual EPROM address 2. Programming the EPROM with downloaded data Freescale Semiconductor Interrupts. Interrupts. 15 before it enters the COP watchdog system. These control bits Chapter 5 Resets and M68HC11E Family Data Sheet, Rev ...

  • Page 48

    ... EPROM latches. Store data to EPROM address Set EPGM bit with ELAT = 1 to enable EPROM programming voltage Delay 2–4 ms Turn off programming voltage and set to READ mode M68HC11E Family Data Sheet, Rev. 5.1 pin PPE M68HC11 Bootstrap Mode has been Freescale Semiconductor ...

  • Page 49

    ... EEPROM. EPGM —EPROM/OTPROM/EEPROM Programming Voltage Enable Bit EPGM can be read any time and can be written only when ELAT = 1 (for EPROM/OTPROM programming) or when EELAT = 1 (for EEPROM programming Programming voltage to EPROM/OTPROM/EEPROM array disconnected 1 = Programming voltage to EPROM/OTPROM/EEPROM array connected Freescale Semiconductor (1) EVEN ELAT ...

  • Page 50

    ... These bits allow selection of either gate stress or drain stress test modes. They can be read and written only in special modes and always read 0 in normal modes ELAT EXCOL EXROW Unimplemented Control Register (EPROG Function Selected 0 0 Normal mode 0 1 Reserved 1 0 Gate stress 1 1 Drain stress M68HC11E Family Data Sheet, Rev. 5 Bit PGM Freescale Semiconductor ...

  • Page 51

    ... CONFIG register. In test or bootstrap modes, write protection is inhibited and BPROT can be written repeatedly. Address ranges for protected areas of EEPROM differ significantly for the MC68HC811E2. Refer to Figure 2-16. Freescale Semiconductor and the frequency of the driving clock. The load depends on the number M68HC11E Family Data Sheet, Rev. 5.1 EEPROM uses MOS ...

  • Page 52

    ... M68HC11E Family Data Sheet, Rev. 5 Bit 0 BPRT2 BPRT1 BPRT0 Block Size 32 bytes 64 bytes 128 bytes 288 bytes Block Size 512 bytes 512 bytes 512 bytes 512 bytes Figure Freescale Semiconductor ...

  • Page 53

    ... ERASE — Erase Mode Select Bit 0 = Normal read or program mode 1 = Erase mode EELAT — EEPROM Latch Control Bit 0 = EEPROM address and data bus configured for normal reads and cannot be programmed 1 = EEPROM address and data bus configured for programming or erasing and cannot be read Freescale Semiconductor (1) ...

  • Page 54

    ... Turn off high voltage and set to READ mode ROW = 1, ERASE = 1, EELAT = 1 Set to ROW erase mode Write any data to any address in ROW ROW = 1, ERASE = 1, EELAT = 1, EPGM = 1 Turn on high voltage Delay 10 ms Turn off high voltage and set to READ mode M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 55

    ... Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR • EB188 — Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR Freescale Semiconductor BYTE = 1, ERASE = 1, EELAT = 1 Set to BYTE erase mode Write any data to address to be erased BYTE = 1, ERASE = 1, EELAT = 1, EPGM = 1 ...

  • Page 56

    ... Operating Modes and On-Chip Memory 56 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 57

    ... A charge pump provides switching voltage to the gates of analog switches in the multiplexer. Charge pump output must stabilize between 7 and 8 volts within up to 100 µs before the converter can be used. The charge pump is enabled by the ADPU bit in the OPTION register. Freescale Semiconductor 3-1. 3-2, which is a functional diagram of an input pin. ...

  • Page 58

    ... ADR2 A/D RESULT 2 ADR3 A/D RESULT ~12V – ~0.7 V – ~0.7V DUMMY N-CHANNEL OUTPUT DEVICE M68HC11E Family Data Sheet, Rev. 5 INTERNAL DATA BUS ADCTL A/D CONTROL ADR4 A/D RESULT 4 DIFFUSION/POLY COUPLER * ð 4 kΩ 400 nA DAC JUNCTION CAPACITANCE LEAKAGE V RL Freescale Semiconductor ...

  • Page 59

    ... The conversion complete flag (CCF) is set after the fourth conversion in a sequence to show the availability of data in the result registers. the timing of a typical sequence. Synchronization is referenced to the system E clock. E CLOCK 12 E CYCLES SAMPLE ANALOG INPUT CONVERT FIRST CHANNEL, UPDATE 0 ADR1 Freescale Semiconductor MSB BIT 6 BIT 5 BIT CYCLES ...

  • Page 60

    ... Chapter 5 Resets and Bit 2 — Not implemented Always reads 0 CR[1:0] — COP Timer Rate Select Bits Refer to Chapter 5 Resets and Interrupts (1) (1) CSEL IRQE DLY CME Interrupts. Interrupts. and Chapter 9 Timing M68HC11E Family Data Sheet, Rev. 5 Bit 0 (1) (1) CR1 CR0 Systems. Freescale Semiconductor ...

  • Page 61

    ... ADCTL register. 2. When SCAN = 1, conversions continue to be performed on the selected channel with the fifth conversion being stored in register ADR1 (overwriting the first conversion result), the sixth conversion overwriting ADR2, and so on. Freescale Semiconductor Table 3-1. Channel Signal ...

  • Page 62

    ... Each time the ADCTL register is overwritten, this bit is automatically cleared to 0 and a conversion sequence is started. In the continuous mode, CCF is set at the end of the first conversion sequence. Bit 6 — Unimplemented Always reads 0 SCAN — Continuous Scan Control Bit SCAN MULT CD 0 Indeterminate after reset M68HC11E Family Data Sheet, Rev. 5 Bit Freescale Semiconductor ...

  • Page 63

    ... CA) have no meaning and the CD and CC bits specify which group of four channels converted. Table 3-2. A/D Converter Channel Selection Channel Select Control Bits CD:CC:CB:CA 10XX 1. Used for factory testing Freescale Semiconductor NOTE Channel Signal 0000 AN0 0001 AN1 0010 ...

  • Page 64

    ... Bit 4 Bit 3 Indeterminate after reset Figure 3-6. Analog-to-Digital Converter Result Registers (ADR1–ADR4) M68HC11E Family Data Sheet, Rev. 5.1 Figure 3-3, which 2 1 Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit 0 Freescale Semiconductor ...

  • Page 65

    ... I/O that are separate from those used for memory. This architecture also allows accessing an operand from an external memory location with no execution time penalty. 4.2 CPU Registers M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. The seven registers, discussed in the following paragraphs, are shown Freescale Semiconductor ...

  • Page 66

    ... CPU registers are pushed onto the stack, and execution continues at the address specified by the vector for the interrupt. 66 M68HC11E Family Data Sheet, Rev. 5.1 4.4 Opcodes and Operands for further Figure 4 Freescale Semiconductor ...

  • Page 67

    ... BSR, BRANCH TO SUBROUTINE MAIN PROGRAM È PC SP–2 $8D = BSR SP–1 SP RTS, RETURN FROM SUBROUTINE MAIN PROGRAM PC $39 = RTS SP SP+1 È SP+2 Freescale Semiconductor RTI, RETURN FROM INTERRUPT INTERRUPT ROUTINE PC STACK 7 0 È SP–2 RTN SP–1 H RTN SP L SWI, SOFTWARE INTERRUPT PC WAI, WAIT FOR INTERRUPT ...

  • Page 68

    ... N bit. 68 4-1. Table 4-1. Reset Vector Comparison POR or RESET Pin Clock Monitor $FFFE, F $FFFC, D $BFFE, F $BFFC, D Table 4-2, which shows what condition codes are M68HC11E Family Data Sheet, Rev. 5.1 COP Watchdog $FFFA, B $BFFA, B Freescale Semiconductor ...

  • Page 69

    ... A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. Because the M68HC11 is an 8-bit CPU, there are no special requirements for alignment of instructions or operands. Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 Data Types Chapter 5 Resets and Interrupts ...

  • Page 70

    ... In most applications, this 256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the memory map can be configured for combinations of internal registers, RAM, or external memory to occupy these addresses. 70 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 71

    ... M68HC11 instructions in all possible addressing modes. For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E-clock cycles. Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 Instruction Set ...

  • Page 72

    ... Freescale Semiconductor ∆ ∆ ∆ — — — — — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ...

  • Page 73

    ... Mask 0 ⇒ M CLR (opr) Clear Memory Byte 0 ⇒ A CLRA Clear Accumulator A 0 ⇒ B CLRB Clear Accumulator B 0 ⇒ V CLV Clear Overflow Flag CMPA (opr) Compare – M Memory Freescale Semiconductor Addressing Instruction Mode Opcode Operand REL 2E rr REL 22 rr REL IMM DIR ...

  • Page 74

    ... Freescale Semiconductor C ∆ ∆ ∆ ∆ ∆ — — — — — — — — ∆ ∆ — — ...

  • Page 75

    ... Logical Shift Left LSLD Logical Shift Left Double LSR (opr) Logical Shift Right 0 b7 LSRA Logical Shift Right LSRB Logical Shift Right Freescale Semiconductor Addressing Instruction Mode Opcode Operand B INH 5C — INH 31 — INH 08 — INH 18 08 — EXT 7E hh IND IND,Y ...

  • Page 76

    ... Freescale Semiconductor ∆ ∆ ∆ ∆ — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ ∆ — — — ∆ ...

  • Page 77

    ... Transfer ⇒ CCR TAP Transfer Register B ⇒ A TBA Transfer TEST TEST (Only in Address Bus Counts Test Modes) CCR ⇒ A TPA Transfer CC Register to A TST (opr) Test for Zero or M – 0 Minus Freescale Semiconductor Addressing Instruction Mode Opcode Operand A IMM DIR EXT ...

  • Page 78

    ... Bit not changed Bit always cleared Bit always set Bit cleared or set, depending on operation Bit can be cleared, cannot become set Freescale Semiconductor — — — — — — — ...

  • Page 79

    ... This external voltage level DD detector, or other external reset circuits, are the usual source of reset in a system. Freescale Semiconductor , the CPU remains in the reset condition until RESET goes to logical 1. NOTE M68HC11E Family Data Sheet, Rev. 5.1 (internal clock ...

  • Page 80

    ... MHz 2.0 MHz M68HC11E Family Data Sheet, Rev. 5.1 Table 5-1. After reset, these XTAL = 16.0 MHz Timeout Timeout – 0 ms, + 8.2 ms 10.923 ms 8.19 ms 43.691 ms 32.8 ms 174.76 ms 131 ms 699.05 ms 524 ms 3.0 MHz 4.0 MHz Freescale Semiconductor ...

  • Page 81

    ... CME bit in the OPTION register disable the clock monitor. After recovery from STOP, set the CME bit to logic 1 to enable the clock monitor. Alternatively, executing a STOP instruction with the CME bit set to logic 1 can be used as a software initiated reset. Freescale Semiconductor 6 5 ...

  • Page 82

    ... See (1) (1) CSEL IRQE DLY CME Converter. Converter. and 15 before it enters the COP watchdog system. These control Table 5-1 M68HC11E Family Data Sheet, Rev. 5 Bit 0 (1) (1) CR1 CR0 Chapter 3 Analog-to-Digital (A/D) for specific timeout settings. Freescale Semiconductor ...

  • Page 83

    ... The stack pointer and other CPU registers are indeterminate immediately after reset; however, the X and I interrupt mask bits in the condition code register (CCR) are set to mask any interrupt requests. Also, the S bit in the CCR is set to inhibit stop mode. Freescale Semiconductor 6 5 ...

  • Page 84

    ... OR, NF, FE, PF, and RAF receive-related status bits in the SCI control register 2 (SCCR2) are cleared. 5.3.8 Serial Peripheral Interface (SPI) The SPI system is disabled by reset. The port pins associated with this function default to being general-purpose I/O lines. 84 M68HC11E Family Data Sheet, Rev. 5.1 Chapter 2 Operating Modes Freescale Semiconductor ...

  • Page 85

    ... Timer input capture 4/output compare 5 11. Timer overflow 12. Pulse accumulator overflow 13. Pulse accumulator input edge 14. SPI transfer complete 15. SCI system (refer to Figure Freescale Semiconductor Chapter 2 Operating Modes and On-Chip Memory 5-7) M68HC11E Family Data Sheet, Rev. 5.1 Reset and Interrupt Priority for a detailed 85 ...

  • Page 86

    ... MDA IRVNE PSEL2 Table 2-1. Hardware Mode Select and Miscellaneous Register (HPRIO) Chapter 2 Operating Modes and On-Chip Memory for more information. for more information. M68HC11E Family Data Sheet, Rev. 5 Bit 0 PSEL2 PSEL1 PSEL0 Summary. Chapter 2 for more information. Freescale Semiconductor for ...

  • Page 87

    ... SCI status register to check for receive errors, then to read the received data from the SCI data register. These steps satisfy the automatic clearing mechanism without requiring special instructions. Freescale Semiconductor Interrupt Source Promoted Timer overflow Pulse accumulator overflow ...

  • Page 88

    ... RIE RIE I TIE TCIE ILIE I SPIE I PAII I PAOVI I TOI I I4/O5I I OC4I I OC3I I OC2I I OC1I I IC3I I IC2I I IC1I I RTII I None X None None None None None None NOCOP None CME None None 5-5. After the CCR value is stacked, the Freescale Semiconductor ...

  • Page 89

    ... Otherwise, it would be almost impossible to determine whether the illegal opcode had been one or two bytes. The stacked return address can be used as a pointer to the illegal opcode so the illegal opcode service routine can evaluate the offending opcode. Freescale Semiconductor (CPU). CPU Registers ...

  • Page 90

    ... SPE control bit. The SCI transmitter is enabled or disabled by the TE bit, and the SCI receiver is enabled or disabled by the RE bit. Therefore, the power consumption in wait is dependent on the particular application. 90 and illustrates interrupt priorities. M68HC11E Family Data Sheet, Rev. 5.1 Figure 5-5 illustrates how the CPU Figure 5 Figure 5-7 shows the resolution of Freescale Semiconductor ...

  • Page 91

    ... POWER-ON RESET (POR) DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) Figure 5-5. Processing Flow Out of Reset (Sheet Freescale Semiconductor EXTERNAL RESET CLOCK MONITOR FAIL (WITH CME = 1) LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFC, $FFFD (VECTOR FETCH) SET BITS S, I, AND X ...

  • Page 92

    ... RESTORE CPU REGISTERS EXECUTE THIS FROM STACK INSTRUCTION 1A M68HC11E Family Data Sheet, Rev. 5.1 STACK CPU REGISTERS STACK CPU REGISTERS ANY N INTERRUPT PENDING? Y SET BIT I IN CCR RESOLVE INTERRUPT PRIORITY AND FETCH VECTOR FOR HIGHEST PENDING SOURCE SEE FIGURE 5–2 Freescale Semiconductor ...

  • Page 93

    ... NO HIGHEST PRIORITY INTERRUPT ? NO IRQ ? NO RTII = IC1I = IC2I = IC3I = OC1I = Figure 5-6. Interrupt Priority Resolution (Sheet Freescale Semiconductor YES YES XIRQ PIN SET X BIT IN CCR LOW ? FETCH VECTOR NO YES FETCH VECTOR YES FETCH VECTOR YES YES REAL-TIME FETCH VECTOR INTERRUPT ? NO YES YES ...

  • Page 94

    ... FETCH VECTOR PAIF = 1? $FFDA, $FFDB N FLAGS Y FETCH VECTOR SPIF = 1? OR MODF = 1? N FETCH VECTOR FETCH VECTOR M68HC11E Family Data Sheet, Rev. 5.1 2B $FFE6, $FFE7 $FFE4, $FFE5 $FFE2, $FFE3 $FFE0, $FFE1 $FFDE, $FFDF $FFD8, $FFD9 $FFD6, $FFD7 $FFF2, $FFF3 END Freescale Semiconductor ...

  • Page 95

    ... To use the IRQ pin as a means of recovering from stop, the I bit in the CCR must be clear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from stop regardless of the state of the X bit in the CCR, although the recovery sequence depends on the state of the X bit set to 0 (XIRQ not Freescale Semiconductor Y RIE = 1? ...

  • Page 96

    ... DLY to be set again by reset, imposing the restart delay. This same delay also applies to power-on reset, regardless of the state of the DLY control bit, but does not apply to a reset while the clocks are running. 96 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 97

    ... In port descriptions indicates this condition. Port pins that are driven to a known logic level during reset are shown with a value of either Some control bits are unaffected by reset. Reset states for these bits are indicated with a U. Freescale Semiconductor for a summary of the ports and their shared functions. Table 6-1. Input/Output Ports ...

  • Page 98

    ... Chapter 9 Timing Systems PA6 PA5 PA4 PA3 OC2 OC3 OC4 IC4/OC5 OC1 OC1 OC1 OC1 PAEWN PAMOD PEDGE DDRA3 NOTE M68HC11E Family Data Sheet, Rev. 5 Bit 0 PA2 PA1 PA0 IC1 IC2 IC3 — — — Bit 0 I4/O5 RTR1 RTR0 Freescale Semiconductor ...

  • Page 99

    ... PC7 Write: Reset: Expanded or special test modes: Read: ADDR7 DATA7 Write: Reset: Figure 6-4. Port C Data Register (PORTC) Address: $1005 Bit 7 Read: PCL7 Write: Reset: Figure 6-5. Port C Latched Register (PORTCL) Freescale Semiconductor PB6 PB5 PB4 PB3 ADDR14 ADDR13 ADDR12 ADDR11 0 ...

  • Page 100

    ... PD5 PD4 — PD5 PD4 — SS SCK DDRD5 DDRD4 DDRD3 M68HC11E Family Data Sheet, Rev. 5 Bit 0 DDRC2 DDRC1 DDRC0 Buffer Bit 0 PD3 PD2 PD1 PD0 PD3 PD2 PD1 PD0 MOSI MISO Tx RxD 2 1 Bit 0 DDRD2 DDRD1 DDRD0 Freescale Semiconductor Figure ...

  • Page 101

    ... PORTC out on all of the port C lines. After the trailing edge of the active signal on STRA, the MCU negates the STRB signal. The 3-state mode variation does not allow part of port used for static inputs while other port C pins are being used for handshake outputs. Refer to the Control Register for further information. Freescale Semiconductor ...

  • Page 102

    ... STRA Inputs latched into Normal output PORTCL on any port, unaffected active edge on in handshake STRA modes Driven as outputs if STRA at active Normal output level; follows port, unaffected DDRC in handshake if STRA not at modes Follow active level DDRC Bit 0 PLS EGA INVB Freescale Semiconductor ...

  • Page 103

    ... STRA falling edge selected, high level activates port C outputs (output handshake STRA rising edge selected, low level activates port C outputs (output handshake) INVB — Invert Strobe B Bit 0 = Active level is logic Active level is logic 1. Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 Parallel I/O Control Register 103 ...

  • Page 104

    ... Parallel Input/Output (I/O) Ports 104 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 105

    ... The block diagram, Figure 7-1, shows the transmit serial shift register and the buffer logic at the top of the figure. Freescale Semiconductor Figure 7-8 and 7.7.5 Baud Rate M68HC11E Family Data Sheet, Rev. 5.1 Register ...

  • Page 106

    ... FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCSR INTERRUPT STATUS TDRE TIE TC TCIE SCCR2 SCI CONTROL 2 for an example of connecting TxD to a PC. M68HC11E Family Data Sheet, Rev. 5.1 DDD1 SEE NOTE PD1 PIN BUFFER TxD AND CONTROL INTERNAL DATA BUS Freescale Semiconductor ...

  • Page 107

    ... RWU bit so that the first frame of the next message can be received. This type of receiver wakeup requires a minimum of one idle-line frame time between messages and no idle time between frames in a message. Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 Receive Operation ...

  • Page 108

    ... RIE IDLE ILIE OR RIE SCCR2 SCI CONTROL 2 for an example of connecting RxD to a PC. Figure 7-2. SCI Receiver Block Diagram M68HC11E Family Data Sheet, Rev. 5.1 10 (11) - BIT Rx SHIFT REGISTER ( MSB ALL 1s RWU 8 SCDR Rx BUFFER READ ONLY 8 8 INTERNAL DATA BUS Freescale Semiconductor ...

  • Page 109

    ... The SCI registers are the same for all M68HC11 E-series devices with one exception. The SCI system for MC68HC(7)11E20 contains an extra bit in the BAUD register that provides a greater selection of baud prescaler rates. Refer to 7.7.5 Baud Rate Freescale Semiconductor Register, Figure 7-8, and M68HC11E Family Data Sheet, Rev ...

  • Page 110

    ... WAKE — Wakeup by Address Mark/Idle Bit 0 = Wakeup by IDLE line recognition 1 = Wakeup by address mark (most significant data bit set) Bits [2:0] — Unimplemented Always read 0 110 R6/T6 R5/T5 R4/T4 R3/T3 Indeterminate after reset WAKE M68HC11E Family Data Sheet, Rev. 5 Bit 0 R2/T2 R1/T1 R0/ Bit Freescale Semiconductor ...

  • Page 111

    ... SBK bit is set, break characters are queued and sent. More than one break may be sent if the transmitter is idle at the time the SBK bit is toggled on and off, as the baud rate clock edge could occur between writing the 1 and writing the 0 to SBK Break generator off 1 = Break codes generated Freescale Semiconductor ...

  • Page 112

    ... Overrun detected NF — Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR with NF set and then reading SCDR Unanimous decision 1 = Noise detected 112 RDRF IDLE M68HC11E Family Data Sheet, Rev. 5 Bit Freescale Semiconductor ...

  • Page 113

    ... SCP2 applies to MC68HC(7)11E20 only. When SCP2 = 1, SCP[1:0] must equal 0s. Any other values for SCP[1:0] are not decoded in the prescaler and the results are unpredictable. Refer to RCKB — SCI Baud Rate Clock Check Bit (Test) See Table 7-1. Freescale Semiconductor SCP2 SCP1 ...

  • Page 114

    ... Freescale Semiconductor 16.00 4.00 250000 125000 62500 31250 15625 7813 3906 1953 83333 41667 20833 10417 5208 2604 1302 651 62500 31250 15625 7813 3906 1953 ...

  • Page 115

    ... The rate select bits determine additional divide by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock is the result of dividing the RT clock by 16. EXTAL OSCILLATOR CLOCK GENERATOR XTAL Figure 7-8. SCI Baud Rate Generator Block Diagram Freescale Semiconductor INTERNAL BUS CLOCK (PH2) AND (÷4) ÷ ...

  • Page 116

    ... Generator Block Diagram M68HC11E Family Data Sheet, Rev. 5.1 ÷ ÷ ÷ SCP[2:0]* 0:1:0 0:1:1 1:0:0 ÷ 16 SCI TRANSMIT BAUD RATE (1X) SCI RECEIVE BAUD RATE (16X) Freescale Semiconductor ...

  • Page 117

    ... The IDLE flag is set only after the RxD line has been busy and becomes idle, which prevents repeated interrupts for the whole time RxD remains idle. Freescale Semiconductor Figure 7-10, which shows SCI interrupt arbitration. ...

  • Page 118

    ... Serial Communications Interface (SCI) BEGIN FLAG Y RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 7-10. Interrupt Source Resolution Within SCI 118 Y RIE = TIE = ILIE = 1? N M68HC11E Family Data Sheet, Rev. 5 TCIE = VALID SCI REQUEST Freescale Semiconductor ...

  • Page 119

    ... SPI device; slave devices that are not selected do not interfere with SPI bus activities master SPI device, the select line can optionally be used to indicate a multiple master bus contention. Refer to Figure 8-2. Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 119 ...

  • Page 120

    ... LSB 8--BIT SHIFT REGISTER READ DATA BUFFER CLOCK CLOCK LOGIC MSTR SPE SPI CONTROL REGISTER INTERNAL DATA BUS Figure 8-1. SPI Block Diagram M68HC11E Family Data Sheet, Rev. 5.1 S MISO PD2 M M MOSI PD3 S S SCK PD4 M SS PD5 Freescale Semiconductor ...

  • Page 121

    ... The MOSI line is the second of the two unidirectional serial data signals output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Freescale Semiconductor 1 2 ...

  • Page 122

    ... SPDR cause data to be written directly into the SPI shift register. Because this write corrupts any transfer in progress, a write collision error is generated. The transfer continues undisturbed, and the write data that caused the error is not written to the shifter. 122 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 123

    ... DDRD bit 5 is set, then the port D bit 5 pin becomes a general-purpose output instead of the SS input SPI system disabled 1 = SPI system enabled DWOM — Port D Wired-OR Mode Bit DWOM affects all port D pins Normal CMOS outputs 1 = Open-drain outputs Freescale Semiconductor SPE DWOM MSTR ...

  • Page 124

    ... SPI System Errors. M68HC11E Family Data Sheet, Rev. 5.1 Figure 8-2 Figure 8-2 Table 8-1. Frequency at Frequency MHz ( MHz Baud) (Baud) 1.5 MHz 2 MHz 750 kHz 1 MHz 187.5 kHz 250 kHz 93.8 kHz 125 kHz 2 1 Bit Freescale Semiconductor and 8.4 ...

  • Page 125

    ... Address: $102A Bit 7 Read: Bit 7 Write: Reset: Figure 8-5. Serial Peripheral Data I/O Register (SPDR) SPI is double buffered in and single buffered out. Freescale Semiconductor Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset M68HC11E Family Data Sheet, Rev. 5.1 SPI Registers 8 ...

  • Page 126

    ... Serial Peripheral Interface (SPI) 126 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 127

    ... If the COP is allowed to time out, a reset is generated, which drives the RESET pin low to reset the MCU and the external system. Refer to Table 9-1 Freescale Semiconductor tapped off of the free-running counter chain. The COP for crystal-related frequencies and periods. ...

  • Page 128

    ... TIMER RESET Figure 9-1. Timer Clock Divider Chains M68HC11E Family Data Sheet, Rev. 5 CLOCK INTERNAL BUS CLOCK (PH2) SPI SCI RECEIVER CLOCK ÷16 SCI TRANSMIT CLOCK PULSE ACCUMULATOR REAL-TIME INTERRUPT FF2 S Q FORCE R COP Q RESET E SERIES TIM DIV CHAIN Freescale Semiconductor ...

  • Page 129

    ... Because these delays offset each other when the time between two edges is being measured, the delay can be ignored. When an input capture is being used with an output compare, there is a similar delay between the actual compare point and when the output pin changes state. Freescale Semiconductor Table 9-1. Timer Summary XTAL Frequencies 4 ...

  • Page 130

    ... ACCUMULATOR OC1I 8 FUNCTIONS PA7/OC1/ BIT 7 OC2I 7 PA6/OC2/ BIT 6 OC3I 6 PA5/OC3/ BIT 5 OC4I 5 PA4/OC4/ BIT 4 I4/O5I 4 PA3/OC5/ BIT 3 IC4/OC1 IC1I 3 BIT 2 PA2/IC1 IC2I 2 BIT 1 PA1/IC2 IC3I 1 BIT 0 PA0/IC3 TMSK 1 PORT A PIN CONTROL CAPTURE COMPARE BLOCK Freescale Semiconductor PIN PAI OC1 OC1 OC1 ...

  • Page 131

    ... The timer input capture registers are not affected by reset. Input capture values can be read from a pair of 8-bit read-only registers. A read of the high-order byte of an Freescale Semiconductor 6 5 ...

  • Page 132

    ... Indeterminate after reset Address: $1015 Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset M68HC11E Family Data Sheet, Rev. 5 Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit 0 Freescale Semiconductor ...

  • Page 133

    ... In addition to an interrupt, a specified action can be initiated at one or more timer output pins. For OC[5:2], the pin action is controlled by pairs of bits (OMx and OLx) in the TCTL1 register. The output action is taken on each successful compare, regardless of whether or not the OCxF flag in the TFLG1 register was previously cleared. Freescale Semiconductor Accumulator. Address: $101E 6 ...

  • Page 134

    ... Address: $1017 Bit 6 Bit 5 Bit 4 Bit Address: $1018 Bit 14 Bit 13 Bit 12 Bit Address: $1019 Bit 6 Bit 5 Bit 4 Bit M68HC11E Family Data Sheet, Rev. 5 Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...

  • Page 135

    ... Address: $100B Bit 7 Read: FOC1 Write: Reset Unimplemented Figure 9-12. Timer Compare Force Register (CFORC) Freescale Semiconductor Address: $101A Bit 14 Bit 13 Bit 12 Bit ...

  • Page 136

    ... Figure 9-14. Output Compare 1 Data Register (OC1D) If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares. Bits [2:0] — Unimplemented Always read 0 136 OC1M6 OC1M5 OC1M4 OC1M3 OC1D6 OC1D5 OC1D4 OC1D3 M68HC11E Family Data Sheet, Rev. 5 Bit Bit Freescale Semiconductor ...

  • Page 137

    ... OL[2:5] — Output Level Bits These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to Table 9-3. Timer Output Compare Actions OMx Freescale Semiconductor Address: $100E Bit 14 Bit 13 Bit 12 ...

  • Page 138

    ... IC1F–IC3F — Input Capture x Flag Set each time a selected active edge is detected on the ICx input line 138 OC2I OC3I OC4I I4/O5I NOTE OC2F OC3F OC4F I4/O5F M68HC11E Family Data Sheet, Rev. 5 Bit 0 IC1I IC2I IC3I Bit 0 IC1F IC2F IC3F Freescale Semiconductor ...

  • Page 139

    ... These bits are used to select the prescaler divide-by ratio. In normal modes, PR[1:0] can be written only once, and the write must be within 64 cycles after reset. Refer to specific timing values. Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2 enable the corresponding interrupt sources. Freescale Semiconductor ...

  • Page 140

    ... This clock causes the time between successive RTI timeouts constant that is 140 RTIF PAOVF PAIF (RTI). Table 9-5. RTI Rates MHz 2.731 ms 4.096 ms 5.461 ms 8.192 ms 16.384 ms 32.768 ms M68HC11E Family Data Sheet, Rev. 5 Bit MHz MHz 13 8.192 ms (E 16.384 ms (E 32.768 ms (E 65.536 ms (E/2 ) Freescale Semiconductor Table 9-5, ...

  • Page 141

    ... Pulse Accumulator. Bits [3:2] — Unimplemented Always read 0 PR[1:0] — Timer Prescaler Select Bits Refer to Table 9-4. Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2 enable the corresponding interrupt sources. Freescale Semiconductor 2, and RTI PAOVI PAII 0 ...

  • Page 142

    ... PAEN — Pulse Accumulator System Enable Bit Refer to 9.7 Pulse Accumulator. PAMOD — Pulse Accumulator Mode Bit Refer to 9.7 Pulse Accumulator. 142 RTIF PAOVF PAIF PAEN PAMOD PEDGE DDRA3 Ports. M68HC11E Family Data Sheet, Rev. 5 Bit Bit 0 I4/O5 RTR1 RTR0 Freescale Semiconductor ...

  • Page 143

    ... MHz 12.0 MHz Pulse accumulator control bits are also located within two timer registers, TMSK2 and TFLG2, as described in the following paragraphs. Freescale Semiconductor Computer Operating Properly (COP) Watchdog Function Ports. rate clock that is compensated independent of the timer prescaler. Chapter 5 Resets and Interrupts Figure 9-24 ...

  • Page 144

    ... PAEN CLOCK : 2 1 MUX DATA BUS PAEN PACTL CONTROL INTERNAL DATA BUS Figure 9-24. Pulse Accumulator M68HC11E Family Data Sheet, Rev. 5.1 PAOVI PAOVF 1 INTERRUPT REQUESTS PAII PAIF 2 TFLG2 INTERRUPT STATUS DISABLE FLAG SETTING OVERFLOW PACNT 8-BIT COUNTER ENABLE Freescale Semiconductor ...

  • Page 145

    ... DDRA3 — Data Direction for Port A Bit 3 Refer to Chapter 6 Parallel Input/Output (I/O) I4/O5 — Input Capture 4/Output Compare 5 Bit 0 = Output compare 5 function enable (no IC4 Input capture 4 function enable (no OC5) RTR[1:0] — RTI Interrupt Rate Select Bits Refer to 9.5 Real-Time Interrupt Freescale Semiconductor PAEN PAMOD PEDGE DDRA3 ...

  • Page 146

    ... PAOVF is set. Before leaving the interrupt service routine, software must clear PAOVF by writing to the TFLG2 register. 146 Bit 6 Bit 5 Bit 4 Bit 3 Indeterminate after reset RTII PAOVI PAII RTIF PAOVF PAIF M68HC11E Family Data Sheet, Rev. 5 Bit 0 Bit 2 Bit 1 Bit Bit 0 PR1 PR0 Bit Freescale Semiconductor ...

  • Page 147

    ... PAIF bit must be polled by user software to determine when an edge has occurred. When the PAII control bit is set, a hardware interrupt request is generated each time PAIF is set. Before leaving the interrupt service routine, software must clear PAIF by writing to the TFLG2 register. Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 Pulse Accumulator ...

  • Page 148

    ... Timing Systems 148 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 149

    ... For proper operation recommended that V ≤ Out inputs are connected to an appropriate logic voltage level (for example, either Freescale Semiconductor NOTE Characteristics, 10.6 Supply Currents and 10.7 MC68L11E9/E20 DC Electrical , and ...

  • Page 150

    ... V DD Symbol Value + (P × Θ User-determined Θ INT I 273° × INT User-determined I/O × 273° Θ × (at equilibrium). Use this value D Freescale Semiconductor Unit °C V Unit °C °C °C W/°C ...

  • Page 151

    ... All outputs except PD[4:1] PD[4:1] = 5.0 Vdc ± 10 Vdc specification for RESET and MODA is not applicable because they are open-drain pins cable to ports C and D in wired-OR mode. 3. Refer to 10.13 Analog-to-Digital Converter Characteristics acteristics for leakage current for port E. Freescale Semiconductor (1) Symbol ...

  • Page 152

    ... V V – 0 loads 152 (1) Symbol IDD S IDD unless otherwise noted M68HC11E Family Data Sheet, Rev. 5.1 Min Max Unit — 15 — — 27 — 35 — 6 — — 10 — 20 — 25 µA — 50 — 100 — 85 — 150 mW — 150 — 195 Freescale Semiconductor ...

  • Page 153

    ... PD[4: 3.0 Vdc to 5.5 Vdc Vdc specification for RESET and MODA is not applicable because they are open-drain pins cable to ports C and D in wired-OR mode. 3. Refer to 10.13 Analog-to-Digital Converter Characteristics acteristics for leakage current for port E. Freescale Semiconductor MC68L11E9/E20 DC Electrical Characteristics (1) Symbol ...

  • Page 154

    ... EXTAL is driven with a square wave, and t = 500 ns for 2 MHz rating CYC t = 333 ns for 3 MHz rating CYC ≤ 0 ≥ – 0 loads 154 (1) Symbol IDD S IDD unless otherwise noted M68HC11E Family Data Sheet, Rev. 5.1 1 MHz 2 MHz Unit 1 2.5 5 µ 150 21 42 Freescale Semiconductor ...

  • Page 155

    ... AC TESTING Notes: 1. Full test loads are applied during all dc electrical tests and ac timing measurements. 2. During ac timing measurements, inputs are driven to 0.4 volts and V measurements are taken at 20% and 70 Freescale Semiconductor MC68L11E9/E20 Supply Currents and Power Dissipation 0.4 VOLTS 0.4 VOLTS ~ V SS ...

  • Page 156

    ... V , unless oth Chapter 5 Freescale Semiconductor Unit MHz ns MHz MHz ns t CYC t CYC CYC ns ...

  • Page 157

    ... PA[2:0] (2) PA[2:0] (1) (3) PA7 (2) (3) PA7 Notes : 1. Rising edge sensitive input 2. Falling edge sensitive input 3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2. Freescale Semiconductor (1) (2) Symbol all timing is shown with respect to 20 TIM Figure 10-2. Timer Inputs M68HC11E Family Data Sheet, Rev ...

  • Page 158

    V DD EXTAL 4064 t CYC E RESET MODA, MODB FFFE FFFE FFFE ADDRESS Figure 10-3. POR External Reset Timing Diagram t PCSU PW RSTL t MPS NEW FFFE FFFF FFFE FFFE FFFE PC t MPH NEW FFFE FFFE FFFF ...

  • Page 159

    INTERNAL CLOCKS 1 IRQ PW IRQ IRQ or XIRQ t STOPDELAY E STOP STOP 4 ADDRESS ADDR ADDR + 1 STOP STOP 5 ADDRESS ADDR ADDR + 1 Notes : 1. Edge Sensitive IRQ pin (IRQE bit = 1) 2. ...

  • Page 160

    E IRQ, XIRQ, OR INTERNAL INTERRUPTS WAIT WAIT ADDRESS SP SP – 1 ADDR ADDR + 1 PCL PCH, YL, YH, XL, XH CCR STACK REGISTERS R/W Note: RESET also causes recovery from WAIT. Figure 10-5. WAIT Recovery ...

  • Page 161

    E t PCSU 1 IRQ PW IRQ 2 IRQ , XIRQ, OR INTERNAL INTERRUPT NEXT NEXT ADDRESS SP SP – 1 OPCODE DATA – – PCL CODE R/W Notes : 1. Edge sensitive IRQ pin (IRQE ...

  • Page 162

    ... V , unless DD DD Freescale Semiconductor ...

  • Page 163

    ... Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers, respec- tively this setup time is met, STRB acknowledges in the next cycle not met, the response may be delayed one more cycle. Freescale Semiconductor (1) (2) Symbol ...

  • Page 164

    ... MCU WRITE TO PORT PWD PWD t t “READY” DEB DEB "READY" AES AES M68HC11E Family Data Sheet, Rev. 5.1 NEW DATA VALID NEW DATA VALID t t DEB DEB (1) 1 READ PORTCL READ PORTCL t t DEB DEB PORT C INPUT HNDSHK TIM Freescale Semiconductor ...

  • Page 165

    ... After reading PIOC with STAF set 1. After reading PIOC with STAF set 2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1). 2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1). Figure 10-13. 3-State Variation of Output Handshake Timing Diagram Freescale Semiconductor ( ...

  • Page 166

    ... V V — — — — — — +32 t — CYC CYC Guaranteed — — — — — — — — — typical — — — 400 400 — 1.0 1 ±10%. R Freescale Semiconductor Uni t Bits +0 +32 µs — Hex Hex µ µA ...

  • Page 167

    ... PE[7:0] Input leakage on A/D pins PE[7:0] Input leakage 3.0 Vdc to 5.5 Vdc Vdc Source impedances greater than 10 kΩ affect accuracy adversely because of input leakage. Freescale Semiconductor MC68L11E9/E20 Analog-to-Digital Converter Characteristics (2) Parameter V SS and 750 kHz ≤ E ≤ 2.0 MHz, unless otherwise noted ...

  • Page 168

    ... V , unless oth Freescale Semiconductor Unit MHz ...

  • Page 169

    ... To recalculate the approximate bus timing values, substitute the following expressions in place of 1 the above formulas, where applicable: CYC (a) (1–dc) × 1/4 t CYC (b) dc × 1/4 t CYC Where the decimal value of duty cycle percentage (high time). Freescale Semiconductor MC68L11E9/E20 Expansion Bus Timing Characteristics (1) –25 ns CYC –30 ns CYC = 1/8 t –30 ns CYC ...

  • Page 170

    ... Note: Measurement points shown are 20% and 70 NOTE: Measurement points shown are 20% and 70 Figure 10-14. Multiplexed Expansion Bus Timing Diagram 170 ADDRESS ADDRESS 19 19 ADDRESS ADDRESS M68HC11E Family Data Sheet, Rev. 5 DATA DATA 21 21 DATA DATA MUX BUS TIM Freescale Semiconductor ...

  • Page 171

    ... Data hold time (outputs) 11 (after enable edge) = 5.0 Vdc ±10 Vdc wise noted 2. Time to data active from high-impedance state 3. Assumes 200 pF load on SCK, MOSI, and MISO pins Freescale Semiconductor Serial Peripheral Interface Timing Characteristics E9 Symbol Min 333 CYC f ...

  • Page 172

    ... CYC CYC 1/2 — — t –30 CYC t –30 CYC 64 t CYC CYC 1/2 — — t –30 CYC — 40 — — 40 — — 40 — — 40 — — — 60 — 0 — and 70 unless DD DD Freescale Semiconductor Unit MHz ns MHz t CYC t CYC t CYC ...

  • Page 173

    ... CPOL = 0 INPUT SCK CPOL = 1 OUTPUT MISO INPUT MOSI OUTPUT Note: This first clock edge is generated internally but is not seen at the SCK pin. Figure 10-15. SPI Timing Diagram (Sheet Freescale Semiconductor MC68L11E9/E20 Serial Peirpheral Interface Characteristics SS IS HELD HIGH ON MASTER MSB IN BIT ...

  • Page 174

    ... Figure 11-15. SPI Timing Diagram (Sheet 174 BIT MSB OUT 10 7 BIT SPI Slave Timing (CPHA = BIT MSB OUT SLAVE MSB IN BIT SPI Slave Timing (CPHA = 1) M68HC11E Family Data Sheet, Rev. 5 SEE SLAVE LSB OUT NOTE 11 11 LSB SLAVE LSB OUT 11 LSB IN Freescale Semiconductor ...

  • Page 175

    ... For more information please refer to MC68HC711E9 8-Bit Microcontroller Unit Mask Set Errata 3 (Freescale document order number 68HC711E9MSE3. 3. Typically, a 1-kΩ series resistor is sufficient to limit the programming current for the MC68HC711E9. A 100-Ω series resis- tor is sufficient to limit the programming current for the MC68HC711E20. Freescale Semiconductor Temperature Range –40 to 85°C 10 ...

  • Page 176

    ... Electrical Characteristics 176 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 177

    ... DIP (.100-inch lead spacing), MC68HC811E2 only 11.2 Standard Device Ordering Information Description 52-pin plastic leaded chip carrier (PLCC) BUFFALO ROM No ROM No ROM, no EEPROM Freescale Semiconductor CONFIG Temperature $0F –40°C to +85°C –40°C to +85°C $0D –40°C to +105°C – ...

  • Page 178

    ... M68HC11E Family Data Sheet, Rev. 5.1 Frequency MC Order Number 2 MHz MC68HC711E9CFN2 3 MHz MC68HC711E9CFN3 2 MHz MC68HC711E9VFN2 2 MHz MC68HC711E9MFN2 2 MHz MC68S711E9CFN2 3 MHz MC68HC711E20FN3 2 MHz MC68HC711E20CFN2 3 MHz MC68HC711E20CFN3 2 MHz MC68HC711E20VFN2 2 MHz MC68HC711E20MFN2 2 MHz MC68HC811E2FN2 2 MHz MC68HC811E2CFN2 2 MHz MC68HC811E2VFN2 2 MHz MC68HC811E2MFN2 2 MHz MC68HC11E9BCFU2 3 MHz MC68HC11E9BCFU3 2 MHz ...

  • Page 179

    ... BUFFALO ROM No ROM No ROM, no EEPROM 11.3 Custom ROM Device Ordering Information Description 52-pin plastic leaded chip carrier (PLCC) Custom ROM Freescale Semiconductor CONFIG Temperature –40°C to +85°C $0F –40°C to +105°C –40°C to +125°C 0°C o +70°°C – ...

  • Page 180

    ... MHz –40°C to +125°C 2 MHz M68HC11E Family Data Sheet, Rev. 5.1 MC Order Number MC68HC11E20FN3 MC68HC11E20CFN2 MC68HC11E20CFN3 MC68HC11E20VFN2 MC68HC11E20MFN2 MC68HC11E9FU3 MC68HC11E9CFU2 MC68HC11E9CFU3 MC68HC11E9VFU2 MC68HC11E9MFU2 MC68HC11E20FU3 MC68HC11E20CFU2 MC68HC11E20CFU3 MC68HC11E20VFU2 MC68HC11E20MFU2 MC68HC11E9PB3 MC68HC11E9CPB2 MC68HC11E9CPB3 MC68HC11E9VPB2 MC68HC11E9MPB2 MC68HC11E9B3 MC68HC11E9CB2 MC68HC11E9CB3 MC68HC11E9VB2 MC68HC11E9MB2 Freescale Semiconductor ...

  • Page 181

    ... Custom ROM No ROM No ROM, no EEPROM 56-pin dual in-line package with 0.70-inch lead spacing (SDIP) Custom ROM No ROM No ROM, no EEPROM Freescale Semiconductor Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc) Temperature Frequency 2 MHz –20°C to +70°C 2 MHz 2 MHz 2 MHz – ...

  • Page 182

    ... U 0.750 0.756 19.05 19.20 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0. 0.710 0.730 18.04 18.54 K1 0.040 ––– 1.02 ––– Freescale Semiconductor S ...

  • Page 183

    ... Windowed Ceramic-Leaded Chip Carrier (Case 778B) -A- R 0.51 (0.020 Freescale Semiconductor 52-Pin Windowed Ceramic-Leaded Chip Carrier (Case 778B) 0.51 (0.020 - 0.15 (0.006) -T- SEATING PLANE 0.18 (0.007 M68HC11E Family Data Sheet, Rev. 5.1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. ...

  • Page 184

    ... REF 0.472 REF 0.130 0.170 0.005 0.007 P 0.40 BSC 0.016 BSC 0.13 0.30 0.005 0.012 S 16.20 16.60 0.638 0.654 T 0.20 REF 0.008 REF U 0 ––– 0 ––– V 16.20 16.60 0.638 0.654 X 1.10 1.30 0.043 0.051 Freescale Semiconductor ...

  • Page 185

    ... Thin Quad Flat Pack (Case 848D) 4X 0.20 (0.008) H L– –L– –H– –T– SEATING PLANE 0.05 (0.002 Freescale Semiconductor 4X TIPS N 0.20 (0.008) T L– VIEW Y 3X –M– –N– θ2 4X 0.10 (0.004) T θ3 4X VIEW θ1 0.25 (0.010) θ ...

  • Page 186

    ... BSC 1.79 BSC J 0.008 0.015 0.20 K 0.115 0.150 2.92 L 0.600 BSC 15.24 BSC M 0 × 15 × 0 × 0.020 0.040 0.51 Freescale Semiconductor MAX 52.45 14.22 5.08 0.56 1.17 0.38 3.43 15 1.02 MAX 62.10 14.22 5.08 0.55 1.52 0.38 3.81 15 × 1.01 ...

  • Page 187

    ... M68HC11 E-series user map that includes 64 Kbytes of emulation RAM • MCU extension input/output (I/O) port for single-chip, expanded, and special-test operation modes • RS-232C terminal and host I/O ports • Logic analyzer connector Freescale Semiconductor Emulation Flex (1) (2) (1) (2) Module Cable ...

  • Page 188

    ... Assembly or C-language source-level debugging with global variable viewing • Host/emulator communications speeds as high as 57,600 baud for quick program loading ® MS-DOS is a registered trademark of Microsoft Corporation. 188 ® disk files to save session history M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 189

    ... Includes programming software and a user’s manual • Includes a +5-volt power cable and a DB9 to DB25 connector adapter ® IBM is a registered trademark145 of International Business Machines Corporation. Freescale Semiconductor SPGMR11 — Serial Programmer for M68HC11 MCUs M68HC11E Family Data Sheet, Rev. 5.1 189 ...

  • Page 190

    ... Development Support 190 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...

  • Page 191

    ... Appendix B EVBU Schematic Refer to Figure B-1 for a schematic diagram of the M68HC11EVBU Universal Evaluation Board. This diagram is included for reference only. Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 191 ...

  • Page 192

    MCU 0.1 µF 1 µF MCU 33 33 MCU 32 32 MCU 31 31 MCU 30 30 MCU 29 29 MCU 28 28 MCU MCU 20 20 MCU 21 ...

  • Page 193

    ... Driving bootstrap mode from another M68HC11 • Driving bootstrap mode from a personal computer • Common bootstrap mode problems • Variations for specific versions of M68HC11 • Commented listings for selected M68HC11 bootstrap ROMs © Freescale Semiconductor, Inc., 2005. All rights reserved. AN1060 Rev. 1.1, 07/2005 ...

  • Page 194

    ... MCU. If any problems appear during product development, diagnostic programs can be downloaded to find the problems, and corrected routines can be downloaded and checked before incorporating them into the main application program. 194 M68HC11 Bootstrap Mode, Rev. 1.1 Freescale Semiconductor ...

  • Page 195

    ... Input Pins MODB MODA Freescale Semiconductor Table 1 Table 1 Table 1. Mode Selection Summary Mode Selected RBOOT Normal single chip Normal expanded Special bootstrap Special test M68HC11 Bootstrap Mode, Rev. 1.1 Bootstrap Mode Logic shows the relationship between the for the following discussion ...

  • Page 196

    ... Refer to the reference numbers in square brackets in Software can change some aspects of the memory map after reset. 196 23 Hz (8.389 MHz). At this crystal frequency, the baud Figure 2 during the following explanation. NOTE M68HC11 Bootstrap Mode, Rev. 1.1 Freescale Semiconductor ...

  • Page 197

    ... EXPANDED CHIP MULTIPLEXED MODA = 0 MODA = 1 MODB = 1 MODB = 1 NOTE: Software can change some aspects of the memory map after reset. Figure 1. MC68HC711E9 Composite Memory Map Freescale Semiconductor Figure 2 Figure 2. The start bit at 1200 baud [5] is 6.5 times as long as EXTERNAL EXTERNAL EXTERNAL SPECIAL SPECIAL ...

  • Page 198

    ... This example 198 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT [2] $FF [5] START [ [9] $C0 or $E0 [10] Listing 3. MC68HC711E9 Bootloader ROM M68HC11 Bootstrap Mode, Rev. 1.1 [4] BIT 7 STOP Tx DATA LINE IDLES HIGH [ BIT 0 BIT 1 [12] [11 Freescale Semiconductor at the ...

  • Page 199

    ... PROGRAM utility routine, which saves the user from having to do this in a downloaded program. The PROGRAM utility is fully explained in step of the bootloader program is to jump to the start of RAM [17], which starts the user’s downloaded program. Freescale Semiconductor EPROM Programming M68HC11 Bootstrap Mode, Rev. 1.1 Main Bootloader Program Common Utility ...

  • Page 200

    ... STORE RECEIVED DATA TO RAM ( ,Y ) [12] TRANSMIT (ECHO) FOR VERIFY [13] POINT AT NEXT RAM LOCATION [14] NO PAST END OF RAM ? YES [15] STAR SET UP FOR PROGRAM UTILITY PROGRAMMING TIME CONSTANT [16 START OF EPROM JUMP TO START [17] OF RAM ($0000) M68HC11 Bootstrap Mode, Rev. 1.1 [2] [4] Freescale Semiconductor ...