N80C251SQ16 Intel, N80C251SQ16 Datasheet - Page 10

• Manufacturer Part Number: N80C251SQ16
• Description: IC MPU 8-BIT 5V 16MHZ 44-PLCC
• Manufacturer: Intel
• Series: 80Cr

Specifications of N80C251SQ16

• Rohs Status: RoHS non-compliant
• Core Processor: MCS 251
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: 804459

10
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
3.0 SIGNALS
A17
A16
A15:8
AD7:0
ALE
CEX4:0
EA#
ECI
INT1:0#
PROG#
P0.7:0
P1.0
P1.1
P1.2
P1.7:3
P2.7:0
†
Signal
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
Name
†
†
Type
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
18th Address Bit (A17). Output to memory as 18th external address
bit (A17) in extended bus applications, depending on the values of bits
RD0 and RD1 in configuration byte UCONFIG0 (see Chapter 4,
“Device Configuration,” of the 8XC251SA/SB/SP/SQ Embedded
Microcontroller User’s Manual). See also RD# and PSEN#.
Address Line 16. See RD#.
Address Lines. Upper address lines for the external bus.
Address/Data Lines. Multiplexed lower address lines and data lines
for external memory.
Address Latch Enable. ALE signals the start of an external bus cycle
and indicates that valid address information is available on lines A15:8
and AD7:0. An external latch can use ALE to demultiplex the address
from the address/data bus.
Programmable Counter Array (PCA) Input/Output Pins. These are
input signals for the PCA capture mode and output signals for the PCA
compare mode and PCA PWM mode.
External Access. Directs program memory accesses to on-chip or off-
chip code memory. For EA# = 0, all program memory accesses are off-
chip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if
the address is within the range of the on-chip
ROM/OTPROM/EPROM; otherwise the access is off-chip. The value
of EA# is latched at reset. For devices without on-chip
ROM/OTPROM/EPROM, EA# must be strapped to ground.
PCA External Clock Input. External clock input to the 16-bit PCA
timer.
External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by
a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are
set by a low level on INT1:0#.
Programming Pulse. The programming pulse is applied to this pin for
programming the on-chip OTPROM.
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.
Table 6. Signal Descriptions
Description
PRELIMINARY
P1.7/CEX4/
WCLK
RD#
P2.7:0
P0.7:0
PROG#
P1.6:3
P1.7/A17/
WAIT#
V
P1.2
P3.3:2
ALE
AD7:0
T2
T2EX
ECI
CEX3:0
CEX4/A17/
WAIT#/
WCLK
A15:8
Alternate
Function
PP