MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 48

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

48
MOTOROLA
MOVE from CCR
MOVE from SR
MOVE to CCR
DIVSL/DIVUL
MOVE to SR
EORI to CCR
MOVE USP
EORI to SR
Instruction
DIVS/DIVU
LPSTOP
ILLEGAL
MOVEA
MOVEC
MOVEM
MOVEA
MOVEP
MOVEQ
MOVE
EXTB
DBcc
EORI
EOR
EXG
LINK
JMP
EXT
JSR
LEA
LSR
LSL
1
1
1
1
1
1
1
# <data>, <ea>
# <data>, CCR
<ea>, Dr : Dq
<ea>, Dr : Dq
Dn, (d16, An)
(d16, An), Dn
# <data>, SR
# <data>, Dn
#<data>, Dn
#<data>, Dn
<ea>, <ea>
CCR, <ea>
<ea>, CCR
SR, <ea>
<ea>, SR
<ea>, Dn
<ea>, Dq
Dn, <ea>
<ea>, An
<ea>, An
list, <ea>
<ea>, list
Dn, label
# <data>
USP, An
An, USP
USP, An
An, USP
Syntax
Rn, Rn
An, # d
Dn, Dn
Dn, Dn
Rc, Rn
Rn, Rc
none
Í
Í
Í
Í
Freescale Semiconductor, Inc.
Dn
Dn
Dn
Table 20 Instruction Set Summary(Continued)
For More Information On This Product,
Go to: www.freescale.com
32/16
64/32
32/32
Operand Size
none
none
16, 32
16, 32
32/32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
8
8
8
16, 32
16, 32
16, 32
none
16
16
32
32
16
16
16
32
32
16
16
16
16
32
32
32
32
8
16 : 16 Destination / Source
32 : 32
32 : 32
16
32
32
32
32
32
32
If condition false, then Dn
if Dn
(signed or unsigned)
Destination / Source
(signed or unsigned)
Source
Data
Source
Source
Rn
Sign extended Destination
Sign extended Destination
SSP
SSP
SSP
Illegal instruction vector address
Destination
SP
<ea>
SP
Data
Source
Source
USP
An
CCR
Source
SR
Source
USP
An
Rc
Rn
Listed registers
Source
Dn [31 : 24]
Dn [15 : 8]
(An
(An
Immediate data
4
4
d)
d
USP
USP
Rn
Rn
Rc
Destination
0
2
4
2
( 1), then PC
Destination
An
An
SR; interrupt mask
Destination
An
X/C
4)
Destination
CCR
SR
SP; PC
SP, An
Destination
Destination
CCR
SR
Listed registers
Dn [31 : 24]; (An
SSP; vector offset
SSP; PC
SSP; SR
(An
PC
(An
Dn [15 : 8]; (An
SR
CCR
Destination
Destination
d
(SP); SP
(SP); destination
d); Dn [23 : 16]
Operation
Destination
d
4); Dn [7 : 0]
Destination
Destination
(SSP);
(SSP);
Destination
1
PC
Destination
Destination
EBI; STOP
d
PC;
d
An, SP
(SSP);
2)
PC
6)
MC68332TS/D
(An
(An
Dn [23 : 16];
PC
X/C
Dn [7 : 0]
d
MC68332
d
d
0
SP
2);
6)