MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet
MC68332ACFC25
Specifications of MC68332ACFC25
Available stocks
Related parts for MC68332ACFC25
MC68332ACFC25 Summary of contents
Page 1
... Freescale Semiconductor © MOTOROLA, INC. 1995 © Freescale Semiconductor, Inc., 2004. All rights reserved. For More Information On This Product, M68300 Family MC68332 User’s Manual Go to: www.freescale.com ...
Page 2
... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
Page 3
... Freescale Semiconductor, Inc. Paragraph SECTION 2NOMENCLATURE 2.1 Symbols and Operators .................................................................................. 2-1 2.2 CPU32 Registers ............................................................................................ 2-2 2.3 Pin and Signal Mnemonics ............................................................................. 2-3 2.4 Register Mnemonics ....................................................................................... 2-4 2.5 Conventions ................................................................................................... 2-5 3.1 MC68332 Features ......................................................................................... 3-1 3.1.1 System Integration Module (SIM) ........................................................... 3-1 3.1.2 Central Processing Unit (CPU) ............................................................... 3-1 3 ...
Page 4
... Freescale Semiconductor, Inc. Paragraph 4.2.10 Software Watchdog ................................................................................ 4-5 4.2.11 Periodic Interrupt Timer .......................................................................... 4-7 4.2.12 Low-Power Stop Operation .................................................................... 4-8 4.2.13 Freeze Operation ................................................................................... 4-9 4.3 System Clock ................................................................................................. 4-9 4.3.1 Clock Sources ...................................................................................... 4-10 4.3.2 Clock Synthesizer Operation ................................................................ 4-10 4.3.3 External Bus Clock ............................................................................... 4-15 4.3.4 Low-Power Operation ...
Page 5
... Freescale Semiconductor, Inc. Paragraph 4.5.6 External Bus Arbitration ........................................................................ 4-35 4.5.6.1 Slave (Factory Test) Mode Arbitration ......................................... 4-36 4.5.6.2 Show Cycles ................................................................................ 4-36 4.6 Reset ............................................................................................................ 4-37 4.6.1 Reset Exception Processing ................................................................ 4-37 4.6.2 Reset Control Logic .............................................................................. 4-38 4.6.3 Reset Mode Selection .......................................................................... 4-38 4.6.3.1 Data Bus Mode Selection ............................................................. 4-39 4 ...
Page 6
... Freescale Semiconductor, Inc. Paragraph 5.2 CPU32 Registers ............................................................................................ 5-2 5.2.1 Data Registers ........................................................................................ 5-3 5.2.2 Address Registers .................................................................................. 5-5 5.2.3 Program Counter .................................................................................... 5-5 5.2.4 Control Registers .................................................................................... 5-5 5.2.4.1 Status Register ............................................................................... 5-5 5.2.4.2 Alternate Function Code Registers ................................................ 5-6 5.2.5 Vector Base Register (VBR) ................................................................... 5-6 5.3 Memory Organization ...
Page 7
... Freescale Semiconductor, Inc. Paragraph 6.2.1.1 Low-Power Stop Operation ........................................................... 6-2 6.2.1.2 Freeze Operation .......................................................................... 6-3 6.2.1.3 QSM Interrupts .............................................................................. 6-3 6.2.2 QSM Pin Control Registers ................................................................... 6-3 6.3 Queued Serial Peripheral Interface ................................................................ 6-4 6.3.1 QSPI Registers ...................................................................................... 6-6 6.3.1.1 Control Registers ........................................................................... 6-7 6.3.1.2 Status Register .............................................................................. 6-7 6 ...
Page 8
... Freescale Semiconductor, Inc. Paragraph 7.2.1 Time Bases ............................................................................................ 7-2 7.2.2 Timer Channels ...................................................................................... 7-2 7.2.3 Scheduler ............................................................................................... 7-2 7.2.4 Microengine ............................................................................................ 7-2 7.2.5 Host Interface ......................................................................................... 7-2 7.2.6 Parameter RAM ...................................................................................... 7-3 7.3 TPU Operation ............................................................................................... 7-3 7.3.1 Event Timing .......................................................................................... 7-3 7.3.2 Channel Orthogonality ............................................................................ 7-4 7.3.3 Interchannel Communication .................................................................. 7-4 7 ...
Page 9
... Freescale Semiconductor, Inc. Paragraph 7.6.1.3 Emulation Control ......................................................................... 7-13 7.6.1.4 Low-Power Stop Control .............................................................. 7-13 7.6.2 Channel Control Registers ................................................................... 7-14 7.6.2.1 Channel Interrupt Enable and Status Registers ........................... 7-14 7.6.2.2 Channel Function Select Registers .............................................. 7-14 7.6.2.3 Host Sequence Registers ............................................................ 7-14 7.6.2.4 Host Service Registers ................................................................. 7-14 7 ...
Page 10
... Freescale Semiconductor, Inc. Paragraph D.2.7 DDRE — Port E Data Direction Register ............................... $YFFA15 D-8 D.2.8 PEPAR — Port E Pin Assignment Register ........................... $YFFA17 D-8 D.2.9 PORTF0/PORTF1 — Port F Data Register...........$YFFA19, $YFFA1B D-9 D.2.10 DDRF — Port F Data Direction Register................................$YFFA1D D-9 D.2.11 PFPAR — ...
Page 11
... Freescale Semiconductor, Inc. Paragraph D.4.11 SPCR1 — QSPI Control Register 1 ....................................$YFFC1A D-26 D.4.12 SPCR2 — QSPI Control Register 2 ................................... $YFFC1C D-27 D.4.13 SPCR3 — QSPI Control Register 3 ............................................ $YFFC1E SPSR — QSPI Status Register $YFFC1F ................................................................ D-27 D.4.14 RR[0:F] — Receive Data RAM........................... $YFFD00–$YFFD0E D-28 D.4.15 TR[0:F] — ...
Page 12
... Freescale Semiconductor, Inc. Paragraph For More Information On This Product, TABLE OF CONTENTS (Continued) Title Go to: www.freescale.com Page MC68332 USER’S MANUAL ...
Page 13
... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 3-1 MCU Block Diagram ....................................................................................... 3-3 3-2 Pin Assignments for 132-Pin Package ........................................................... 3-4 3-3 Pin Assignments for 144-Pin Package ........................................................... 3-5 3-4 Internal Register Memory Map ..................................................................... 3-10 3-5 Overall Memory Map .................................................................................... 3-11 3-6 Separate Supervisor and User Space Map .................................................. 3-12 3-7 Supervisor Space (Separate Program/Data Space) Map ...
Page 14
... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 6-3 QSPI RAM ...................................................................................................... 6-8 6-4 Flowchart of QSPI Initialization Operation .................................................... 6-11 6-5 Flowchart of QSPI Master Operation (Part 1) .............................................. 6-12 6-5 Flowchart of QSPI Master Operation (Part 2) .............................................. 6-13 6-5 Flowchart of QSPI Master Operation (Part 3) .............................................. 6-14 6-6 Flowchart of QSPI Slave Operation (Part 1) ................................................ 6-15 6-6 Flowchart of QSPI Slave Operation (Part 2) ...
Page 15
... Freescale Semiconductor, Inc. Table 3-1 MCU Driver Types........................................................................................... 3-6 3-2 MCU Pin Characteristics ................................................................................. 3-6 3-3 MCU Power Connections ................................................................................ 3-7 3-4 MCU Signal Characteristics ............................................................................ 3-7 3-5 MCU Signal Function ...................................................................................... 3-8 3-6 SIM Reset Mode Selection............................................................................ 3-15 3-7 Module Pin Functions.................................................................................... 3-16 4-1 Show Cycle Enable Bits ...
Page 16
... Freescale Semiconductor, Inc. Table 6-5 Serial Frame Formats.................................................................................... 6-26 6-6 Effect of Parity Checking on Data Size ......................................................... 6-27 7-1 TCR1 Prescaler Control ................................................................................ 7-12 7-2 TCR2 Prescaler Control ................................................................................ 7-13 7-3 Channel Priority Encodings ........................................................................... 7-15 A-1 Maximum Ratings............................................................................................ A-1 A-2 Typical Ratings, 16.78 MHz Operation............................................................ A-2 A-2 a ...
Page 17
... Freescale Semiconductor, Inc. SECTION 1 INTRODUCTION The MC68332, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB). Standardization facilitates rapid development of devices tailored for specific applica- tions ...
Page 18
... Freescale Semiconductor, Inc. 1-2 For More Information On This Product, INTRODUCTION Go to: www.freescale.com MC68332 USER’S MANUAL ...
Page 19
... Freescale Semiconductor, Inc. SECTION 2 NOMENCLATURE The following nomenclature is used throughout the manual. Nomenclature used only in certain sections, such as register bit mnemonics, is defined in those sections. 2.1 Symbols and Operators + — Addition - — Subtraction or negation (two's complement) * — Multiplication / — Division > — Greater < ...
Page 20
... Freescale Semiconductor, Inc. 2.2 CPU32 Registers A6–A0 — Address registers (Index registers) A7 (SSP) — Supervisor Stack Pointer A7 (USP) — User Stack Pointer CCR — Condition code register (user portion of SR) D7–D0 — Data Registers (Index registers) DFC — Alternate function code register PC — ...
Page 21
... Freescale Semiconductor, Inc. 2.3 Pin and Signal Mnemonics ADDR[23:0] — Address Bus AS — Address Strobe AVEC — Autovector BERR — Bus Error BG — Bus Grant BGACK — Bus Grant Acknowledge BKPT — Breakpoint BR — Bus Request CLKOUT — System Clock CS[10:0] — Chip Selects CSBOOT — ...
Page 22
... Freescale Semiconductor, Inc. 2.4 Register Mnemonics CFSR[0:3] — Channel Function Select Registers [0:3] CIER — Channel Interrupt Enable Register CISR — Channel Interrupt Status Register CPR[0:1] — Channel Priority Registers [0:1] CREG — Test Control Register C CR[0:F] — QSM Command RAM CSBARBT — ...
Page 23
... Freescale Semiconductor, Inc. SWSR — Software Watchdog Service Register SYNCR — Clock Synthesizer Control Register SYPCR — System Protection Control Register TCR — TPU Test Configuration Register TICR — TPU Interrupt Configuration Register TPUMCR — TPU Module Configuration Register TRAMBAR — TPURAM Base Address/Status Register TRAMMCR — ...
Page 24
... Freescale Semiconductor, Inc. 2-6 For More Information On This Product, NOMENCLATURE Go to: www.freescale.com MC68332 USER’S MANUAL ...
Page 25
... Freescale Semiconductor, Inc. This section contains information about the entire modular microcontroller. It lists the features of each module, shows device functional divisions and pin assignments, sum- marizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. Timing and electrical specifications for the entire microcontroller and for individual modules are provided in APPENDIX A ELECTRICAL CHARACTERIS- TICS ...
Page 26
... Freescale Semiconductor, Inc. 3.1.4 Queued Serial Module (QSM) • Enhanced Serial Communication Interface (SCI), Universal Asynchronous Re- ceiver Transmitter (UART): Modulus Baud Rate, Parity • Queued Serial Peripheral Interface (SPI): 80-Byte RAM Automatic Transfers • Dual Function I/O Ports • Continuous Cycling, 8–16 Bits per Transfer 3.1.5 Static RAM Module with TPU Emulation Capability (TPURAM) • ...
Page 27
... Freescale Semiconductor, Inc. TPUCH[15:0] TPUCH[15:0] T2CLK T2CLK RXD PQS7/TXD TXD PQS6/PCS3 PCS3 PQS5/PCS2 PCS2 PQS4/PCS1 PCS1 PQS3/PCS0/SS PCS0/SS PQS2/SCK SCK PQS1/MOSI MOSI PQS0/MISO MISO QSM BKPT/DSCLK IFETCH/DSI IPIPE/DSO Figure 3-1 MCU Block Diagram MC68332 USER’S MANUAL For More Information On This Product, ...
Page 28
... Freescale Semiconductor, Inc STBY ADDR1 20 ADDR2 21 ADDR3 22 ADDR4 23 ADDR5 24 ADDR6 25 ADDR7 26 ADDR8 ADDR9 30 ADDR10 31 ADDR11 32 ADDR12 ADDR13 35 ADDR14 36 ADDR15 37 ADDR16 ADDR17 41 ADDR18 42 PQS0/MISO 43 PQS1/MOSI 44 PQS2/SCK 45 PQS3/PCS0/SS 46 PQS4/PCS1 47 PQS5/PCS2 48 PQS6/PCS3 Figure 3-2 Pin Assignments for 132-Pin Package 3-4 For More Information On This Product, ...
Page 29
... Freescale Semiconductor, Inc FC0/CS3 4 FC1/CS4 5 FC2/CS5 ADDR19/CS6 6 7 ADDR20/CS7 ADDR21/CS8 8 9 ADDR22/CS9 10 ADDR23/CS10 T2CLK 14 TPUCH15 TPUCH14 15 16 TPUCH13 TPUCH12 TPUCH11 22 TPUCH10 23 TPUCH9 24 TPUCH8 V 25 DDE V 26 SSE 27 TPUCH7 TPUCH6 28 29 TPUCH5 30 TPUCH4 31 TPUCH3 32 TPUCH2 33 TPUCH1 34 TPUCH0 Figure 3-3 Pin Assignments for 144-Pin Package 3 ...
Page 30
... Freescale Semiconductor, Inc. Type I Output-only signals that are always driven; no external pull-up required Aw O Type A output with weak P-channel pull-up during reset B O Three-state output that includes circuitry to pull up output before high impedance is established, to ensure rapid rise time. An external holding resistor is required to maintain logic level while the pin is in the high-impedance state ...
Page 31
... Freescale Semiconductor, Inc. Table 3-2 MCU Pin Characteristics (Continued) Pin Mnemonic TXD 2 XFC 2 XTAL NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin. 2. EXTAL, XFC, and XTAL are clock reference connections. Table 3-3 MCU Power Connections ...
Page 32
... Freescale Semiconductor, Inc. Table 3-4 MCU Signal Characteristics (Continued) Signal Name IFETCH IPIPE IRQ[7:1] MISO MODCLK MOSI PC[6:0] PCS[3:0] PE[7:0] PF[7:0] PQS[7:0] QUOT RESET RMC R/W RXD SCK SIZ[1:0] SS T2CLK TPUCH[15:0] TSC TXD XFC XTAL Table 3-5 MCU Signal Function Signal Name ...
Page 33
... Freescale Semiconductor, Inc. Table 3-5 MCU Signal Function (Continued) Signal Name Mnemonic Function Codes Freeze FREEZE Halt Instruction Pipeline IPIPE, IFETCH Indicate instruction pipeline activity Interrupt Request Level IRQ[7:1] Master In Slave Out Clock Mode Select MODCLK Master Out Slave In Port C Auxiliary Timer Clock Input ...
Page 34
... Freescale Semiconductor, Inc. 3.6.1 Internal Register Map In Figure 3-4, IMB ADDR[23:20] are represented by the letter Y. The value represent determines the base address of MCU module control registers. In M68300 mi- crocontrollers equal to M111, where M is the logic state of the module mapping (MM) bit in the system integration module configuration register (SIMCR). ...
Page 35
... Freescale Semiconductor, Inc. $ 000000 COMBINED SUPERVISOR AND USER SPACE $7FF000 INTERNAL REGISTERS ( $FF0000 INTERNAL REGISTERS ( $FFFFFF NOTES: 1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset. 2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configure register. ...
Page 36
... Freescale Semiconductor, Inc. $000000 VECTOR OFFSET 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 0038 003C 0040–005C 006C 0064 SUPERVISOR 0068 SPACE 006C 0070 0074 0078 007C 0080–00BC 00C0–00EB 00EC–00FC 0100–03FC ...
Page 37
... Freescale Semiconductor, Inc. VECTOR $000000 OFFSET 0000 0004 VECTOR OFFSET 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 SUPERVISOR 0038 DATA 003C 0040–005C SPACE 006C 0064 0068 006C 0070 0074 0078 007C 0080–00BC 00C0– ...
Page 38
... Freescale Semiconductor, Inc. $000000 USER PROGRAM SPACE $FFFFFF NOTES: 1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset. 2. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally. ...
Page 39
... Freescale Semiconductor, Inc. 3.7 System Reset The following information is a concise reference only. MC68332 system reset is a com- plex operation. To understand operation during and after reset, refer to SECTION 4 SYSTEM INTEGRATION MODULE, paragraph 4.6 Reset for more complete discus- sion of the reset function. ...
Page 40
... Freescale Semiconductor, Inc. 3.7.2 MCU Module Pin Function During Reset Generally, pins associated with modules other than the SIM default to port functions, and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers ...
Page 41
... Freescale Semiconductor, Inc. SECTION 4 SYSTEM INTEGRATION MODULE This section is an overview of SIM function. Refer to the SIM Reference Manual (SIM- RM/AD) for a comprehensive discussion of SIM capabilities. Refer to APPENDIX D REGISTER SUMMARY for information concerning the SIM address map and register structure. 4.1 General The system integration module (SIM) consists of five functional blocks ...
Page 42
... Freescale Semiconductor, Inc. SYSTEM CONFIGURATION AND PROTECTION CLOCK SYNTHESIZER CHIP SELECTS EXTERNAL BUS INTERFACE FACTORY TEST Figure 4-1 System Integration Module Block Diagram 4.2 System Configuration and Protection The system configuration and protection functional block controls module configura- tion, preserves reset status, monitors internal activity, and provides periodic interrupt generation ...
Page 43
... Freescale Semiconductor, Inc. SPURIOUS INTERRUPT MONITOR CLOCK 9 2 PRESCALER Figure 4-2 System Configuration and Protection 4.2.1 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping bit (MM) in the SIM configuration register (SIMCR) determines where the control register block is located in the system memory map. When register addresses range from $7FF000 to $7FFFFF ...
Page 44
... Freescale Semiconductor, Inc. terrupt request is acknowledged, even when there is only a single request pending. For an interrupt to be serviced, the appropriate IARB field must have a non-zero value interrupt request from a module with an IARB field value of %0000 is recognized, the CPU32 processes a spurious interrupt exception. ...
Page 45
... Freescale Semiconductor, Inc. 4.2.7 Bus Monitor The internal bus monitor checks data and size acknowledge (DSACK) or autovector (AVEC) signal response times during normal bus cycles. The monitor asserts the in- ternal bus error (BERR) signal when the response time is excessively long. DSACK and AVEC response times are measured in clock cycles. Maximum allowable response time can be selected by setting the bus monitor timing (BMT) field in the sys- tem protection control register (SYPCR) ...
Page 46
... Freescale Semiconductor, Inc. Perform a software watchdog service sequence as follows: 1. Write $55 to SWSR. 2. Write $AA to SWSR. Both writes must occur before time-out in the order listed, but any number of instruc- tions can be executed between the two writes. Watchdog clock rate is affected by the software watchdog prescale (SWP) and soft- ware watchdog timing (SWT) fields in SYPCR ...
Page 47
... Freescale Semiconductor, Inc. SWP PTP FREEZE CLOCK EXTAL PRESCALER (2 DISABLE LPSTOP SWT1 SWT0 SWE Figure 4-3 Periodic Interrupt Timer and Software Watchdog Timer 4.2.11 Periodic Interrupt Timer The periodic interrupt timer allows the generation of interrupts of specific priority at pre- determined intervals. This capability is often used to schedule control system tasks that must be performed within time constraints ...
Page 48
... Freescale Semiconductor, Inc. Use the following expression to calculate timer period. PIT Period Interrupt priority and vectoring are determined by the values of the periodic interrupt request level (PIRQL) and periodic interrupt vector (PIV) fields in the periodic interrupt control register (PICR). Content of PIRQL is compared to the CPU32 interrupt priority mask to determine whether the interrupt is recognized ...
Page 49
... Freescale Semiconductor, Inc. 4.2.13 Freeze Operation The FREEZE signal halts MCU operations during debugging. FREEZE is asserted in- ternally by the CPU32 if a breakpoint occurs while background mode is enabled. When FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt timer are affected. The halt monitor and spurious interrupt monitor continue to operate normally ...
Page 50
... Freescale Semiconductor, Inc. 4.3.1 Clock Sources The state of the clock mode (MODCLK) pin during reset determines clock source. When MODCLK is held high during reset, the clock synthesizer generates a clock sig- nal from either an internal or an external reference frequency — the clock synthesizer control register (SYNCR) determines operating frequency and mode of operation ...
Page 51
... Freescale Semiconductor, Inc. ply must be used as the V DDSYN be placed as close as possible to the V cy. When an external system clock signal is applied and the PLL is disabled, V should be connected to the V AD) for more information regarding system clock power supply conditioning. A voltage controlled oscillator (VCO) generates the system clock signal. To maintain a 50% clock duty cycle, VCO frequency is either two or four times system clock fre- quency, depending on the state of the X bit in SYNCR ...
Page 52
... Freescale Semiconductor, Inc. When the clock synthesizer is used, control register SYNCR determines operating fre- quency and various modes of operation. The SYNCR W bit controls a three-bit pres- caler in the feedback divider. Setting W increases VCO speed by a factor of four. The SYNCR Y field determines the count modulus for a modulo 64 down counter, causing it to divide by a value ...
Page 53
... Freescale Semiconductor, Inc. Table 4-7 Clock Control Multipliers (Continued) To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell. Modulus Y [W: 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 ...
Page 54
... Freescale Semiconductor, Inc. Table 4-8 System Frequencies from 32.768–kHz Reference To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell. Modulus Y [W: 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 ...
Page 55
... Freescale Semiconductor, Inc. Table 4-8 System Frequencies from 32.768–kHz Reference (Continued) To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell. Modulus Y [W: 101101 101110 101111 110000 110001 110010 110011 110100 110101 ...
Page 56
... Freescale Semiconductor, Inc. During a low-power stop, unless the system clock signal is supplied by an external source and that source is removed, the SIM clock control logic and the SIM clock sig- nal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK ...
Page 57
... Freescale Semiconductor, Inc. 4.4 External Bus Interface The external bus interface (EBI) transfers information between the internal MCU bus and external devices. Figure 4-7 shows a basic system with external memory and pe- ripherals SIZ CLKOUT AS DSACK DS CS3 CS5 IRQ ADDR[23:0] DATA[15:0] MCU ...
Page 58
... Freescale Semiconductor, Inc. 4.4.1 Bus Signals The address bus provides addressing information to external devices. The data bus transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals, one for the address bus and another for the data bus, indicate the validity of an ad- dress and provide timing information for data ...
Page 59
... Freescale Semiconductor, Inc. 4.4.1.6 Size Signals Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during an operand cycle. They are valid while the address strobe (AS) is asserted. Table 4- 10 shows SIZ0 and SIZ1 encoding. Table 4-10 Size Signal Encoding SIZ1 ...
Page 60
... Freescale Semiconductor, Inc. 4.4.1.9 Bus Error Signal The bus error signal (BERR) is asserted when a bus cycle is not properly terminated by DSACK or AVEC assertion. BERR can also be asserted at the same time as DSACK, provided the appropriate timing requirements are met. Refer to 4.5.5 Bus Ex- ception Control Cycles for more information ...
Page 61
... Freescale Semiconductor, Inc. Table 4-12 Effect of DSACK Signals DSACK1 DSACK0 the CPU is executing an instruction that reads a long-word operand from a 16-bit port, the MCU latches the 16 bits of valid data and then runs another bus cycle to ob- tain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles ...
Page 62
... Freescale Semiconductor, Inc. 4.4.4 Misaligned Operands CPU32 architecture uses a basic operand size of 16 bits. An operand is misaligned when it overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even address), the address word and byte boundary. When ADDR0 = 1 (an odd address), the address byte boundary only. A byte operand is aligned at any address ...
Page 63
... Freescale Semiconductor, Inc. Fast-termination cycles, which are two-cycle external accesses with no wait states, use chip-select logic to generate handshaking signals internally. Chip-select logic can also be used to insert wait states before internal generation of handshaking signals. Refer to 4.5.3 Fast Termination Cycles and 4.8 Chip Selects for more information. ...
Page 64
... Freescale Semiconductor, Inc. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. The SIZ signals and ADDR0 are externally decoded to select the active portion of the data bus (refer to 4.4.2 Dynamic Bus Sizing). When AS, DS, and R/W are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle), then asserts a DSACK[1:0] combination that indicates port size ...
Page 65
... Freescale Semiconductor, Inc. MCU ADDRESS DEVICE (S0) 1) SET R/W TO READ 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS AND DS (S1) DECODE DSACK (S3) LATCH DATA (S4) NEGATE AS AND DS (S5) START NEXT CYCLE (S0) Figure 4-9 Word Read Cycle Flowchart 4 ...
Page 66
... Freescale Semiconductor, Inc. MCU ADDRESS DEVICE (S0) 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON ADDR[23:0] 3) DRIVE FUNCTION CODE ON FC[2:0] 4) DRIVE SIZ[1:0] FOR OPERAND SIZE ASSERT AS (S1) PLACE DATA ON DATA[15:0] (S2) ASSERT DS AND WAIT FOR DSACK (S3) OPTIONAL STATE (S4) NO CHANGE TERMINATE OUTPUT TRANSFER (S5) 1) NEGATE DS AND AS ...
Page 67
... Freescale Semiconductor, Inc. When AS, DS, and R/W are valid, a peripheral device either places data on the bus (read cycle) or latches data from the bus (write cycle). At the appropriate time, chip- select logic asserts data and size acknowledge signals. The DSACK option fields in the chip-select option registers determine whether inter- nally generated DSACK or externally generated DSACK are used ...
Page 68
... Freescale Semiconductor, Inc. 4.5.4.1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at a predefined point during system development. Breakpoints can be used alone or in conjunction with the background debugging mode. The following paragraphs discuss breakpoint processing when background de- bugging mode is not enabled. See SECTION 5 CENTRAL PROCESSING UNIT for more information on exception processing and the background debugging mode ...
Page 69
... Freescale Semiconductor, Inc. the tagged instruction is executed, no breakpoint occurs. When BKPT assertion is syn- chronized with an operand fetch, exception processing occurs at the end of the instruc- tion during which BKPT is latched. Refer to the CPU32 Reference Manual (CPU32RM/AD) and the SIM Reference Man- ual (SIMRM/AD) for additional information. ...
Page 70
... Freescale Semiconductor, Inc. CPU32 ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED: 1) SET R/W TO READ 2) SET FUNCTION CODE TO CPU SPACE 3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16] 4) PLACE BREAKPOINT NUMBER ON ADDR[4:2] 5) CLEAR T-BIT (ADDR1) TO ZERO 6) SET SIZE TO WORD 7) ASSERT AS AND DS IF BKPT PIN ASSERTED: 1) SET R/W TO READ ...
Page 71
... Freescale Semiconductor, Inc. 4.5.4.2 LPSTOP Broadcast Cycle Low-power stop is initiated by the CPU32. Individual modules can be stopped by set- ting the STOP bits in each module configuration register, or the SIM can turn off sys- tem clocks after execution of the LPSTOP instruction. When the CPU executes LPSTOP, the LPSTOP broadcast cycle is generated ...
Page 72
... Freescale Semiconductor, Inc. Retry Termination HALT and BERR are asserted in lieu of, at the same time as, or before DSACK or after DSACK; BERR is negated at the same time or after DSACK; HALT may be negated at the same time or after BERR. Table 4-14 shows various combinations of control signal sequences and the resulting bus cycle terminations ...
Page 73
... Freescale Semiconductor, Inc. 4.5.5.1 Bus Errors The CPU32 treats bus errors as a type of exception. Bus error exception processing begins when the CPU detects assertion of the IMB BERR signal (by the internal bus monitor or an external source) while the HALT signal remains negated. ...
Page 74
... Freescale Semiconductor, Inc. Immediately after assertion of a second BERR, the MCU halts and drives the HALT line low. Only a reset can restart a halted MCU. However, bus arbitration can still occur (refer to 4.5.6 External Bus Arbitration). A bus error or address error that occurs after exception processing has been completed (during the execution of the exception han- dler routine, or later) does not cause a double bus fault ...
Page 75
... Freescale Semiconductor, Inc. The halt operation has no effect on bus arbitration (refer to 4.5.6 External Bus Arbi- tration). However, when external bus arbitration occurs while the MCU is halted, ad- dress and control signals go to high-impedance state. If HALT is still asserted when the MCU regains control of the bus, address, function code, size, and read/write sig- nals revert to the previous driven states ...
Page 76
... Freescale Semiconductor, Inc. MCU GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) TERMINATE ARBITRATION 1) NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED) RE-ARBITRATE OR RESUME PROCESSOR OPERATION Figure 4-14 Bus Arbitration Flowchart for Single Request State changes occur on the next rising edge of CLKOUT after the internal signal is val- id ...
Page 77
... Freescale Semiconductor, Inc. Show cycles are controlled by the SHEN field in the SIMCR (refer to 4.2.3 Show In- ternal Cycles). This field is cleared by reset. When show cycles are disabled, the address bus, function codes, size, and read/write signals reflect internal bus activity, but AS and DS are not asserted externally and external data bus pins are in high-im- pedance state during internal accesses ...
Page 78
... Freescale Semiconductor, Inc. 4.6.2 Reset Control Logic SIM reset control logic determines the cause of a reset, synchronizes reset assertion if necessary to the completion of the current bus cycle, and asserts the appropriate re- set lines. Reset control logic can drive four different internal signals. ...
Page 79
... Freescale Semiconductor, Inc. Table 4-16 Reset Mode Selection Mode Select Pin DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA11 MODCLK BKPT 4.6.3.1 Data Bus Mode Selection All data lines have weak internal pull-up drivers. When pins are held high by the inter- nal drivers, the MCU uses a default operating configuration ...
Page 80
... Freescale Semiconductor, Inc. DATA15 • • • • MODE SELECT • • DATA1 LINES DATA0 RESET DS R/W * Optional, to prevent conflict on RESET negation. Figure 4-15 Data Bus Mode Select Conditioning Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC- TERISTICS. Do not confuse pin function with pin electrical state. Refer to 4.6.5 Pin State During Reset for more information ...
Page 81
... Freescale Semiconductor, Inc. 4.6.3.2 Clock Mode Selection The state of the clock mode (MODCLK) pin during reset determines what clock source the MCU uses. When MODCLK is held high during reset, the clock signal is generated from a reference frequency. When MODCLK is held low during reset, the clock syn- thesizer is disabled, and an external system clock signal must be applied ...
Page 82
... Freescale Semiconductor, Inc. Table 4-17 Module Pin Functions Module CPU32 GPT QSM 4.6.5 Pin State During Reset It is important to keep the distinction between pin function and pin electrical state clear. Although control register values and mode select inputs determine pin function, a pin driver can be active, inactive or in high-impedance state while reset occurs ...
Page 83
... Freescale Semiconductor, Inc. Table 4-18 SIM Pin Reset States Mnemonic CS10/ADDR23 CS[9:6]/ADDR[22:19]/PC[6:3] ADDR[18:0] AS/PE5 AVEC/PE2 BERR CSM/BG CSE/BGACK CS0/BR CLKOUT CSBOOT DATA[15:0] DS/PE4 DSACK0/PE0 DSACK1/PE1 CS5/FC2/PC2 FC1/PC1 CS3/FC0/PC0 HALT IRQ[7:1]/PF[7:1] MODCLK/PF0 R/W RESET RMC SIZ[1:0]/PE[7:6] TSC 4.6.5.2 Reset States of Pins Assigned to Other MCU Modules As a rule, module pins that are assigned to general-purpose I/O ports go to active high- impedance state following reset ...
Page 84
... Freescale Semiconductor, Inc internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert RESET until the internal reset signal is negated. After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for ten cycles ...
Page 85
... Freescale Semiconductor, Inc. CLKOUT VCO LOCK V DD RESET BUS CYCLES ADDRESS AND BUS STATE CONTROL SIGNALS UNKNOWN THREE-STATED NOTES: 1. Internal start-up time. 2. SSP fetched fetched. 4. First instruction fetched. Figure 4-16 Power-On Reset 4.6.8 Reset Processing Summary To prevent write cycles in progress from being corrupted, a reset is recognized at the end of a bus cycle, and not at an instruction boundary ...
Page 86
... Freescale Semiconductor, Inc. 4.6.9 Reset Status Register The reset status register (RSR) contains a bit for each reset source in the MCU. When a reset occurs, a bit corresponding to the reset type is set. When multiple causes of reset occur at the same time, more than one bit in RSR may be set. The reset status register is updated by the reset control logic when the RESET signal is released ...
Page 87
... Freescale Semiconductor, Inc. IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected unless a falling edge transition is detected on the IRQ7 line. This prevents redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask changes from %111 to a lower number while IRQ7 is asserted ...
Page 88
... Freescale Semiconductor, Inc. Do not assign the same arbitration priority to more than one module. When two or more IARB fields have the same nonzero value, the CPU32 interprets multiple vector numbers at the same time, with un- predictable consequences. Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration between internal and external interrupt requests ...
Page 89
... Freescale Semiconductor, Inc. B. The processor state is stacked. The S bit in the status register is set, establish- ing supervisor access level, and bits T1 and T0 are cleared, disabling tracing. C. The interrupt acknowledge cycle begins: 1. FC[2:0] are driven to %111 (CPU space) encoding. 2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge CPU space cycle ...
Page 90
... Freescale Semiconductor, Inc SIZ CLKOUT AS DSACK DS CS3 CS5 IRQ ADDR[23:0] DATA[15:0] MCU CSBOOT R/W 1. Can be decoded to provide additional address space. 2. Varies depending upon peripheral memory size. Figure 4-17 Basic MCU System Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals ...
Page 91
... Freescale Semiconductor, Inc. in the corresponding option register is programmed to a nonzero value, selecting a transfer size. The chip-select option must not be written until a base address has been written to a proper base address register. CSBOOT is automatically asserted out of reset. Alternate functions for chip-select pins are enabled if appropriate data bus pins are held low at the release of the reset signal (refer to 4 ...
Page 92
... Freescale Semiconductor, Inc. 4.8.1.1 Chip-Select Pin Assignment Registers The pin assignment registers contain twelve 2-bit fields (CS[10:0] and CSBOOT) that determine the functions of the chip-select pins. Each pin has two or three possible functions, as shown in Table 4-19. Table 4-19 Chip-Select Pin Functions ...
Page 93
... Freescale Semiconductor, Inc. A pin programmed as a discrete output drives an external signal to the value specified in the pin data register. No discrete output function is available on pins CSBOOT, BR, BG, or BGACK. ADDR23 provides ECLK output rather than a discrete output signal. When a pin is programmed for discrete output or alternate function, internal chip-select logic still functions and can be used to generate DSACK or AVEC internally on an ad- dress and control signal match ...
Page 94
... Freescale Semiconductor, Inc. Table 4-22 Option Register Function Summary MODE BYTE R ASYNC Disable 00 = Rsvd SYNC 01 = Lower 01 = Read Upper 10 = Write *11 = Both 11 = Both *Use this value when function is not required for chip-select operation. The MODE bit determines whether chip-select assertion simulates an asynchronous bus cycle synchronized to the M6800-type bus clock signal (ECLK) available on ADDR23 (refer to 4 ...
Page 95
... Freescale Semiconductor, Inc. to %00 (CPU space), interrupt priority (ADDR[3:1]) is compared to IPL value. If the val- ues are the same, and other option register constraints are satisfied, a chip select sig- nal is asserted. This field only affects the response of chip selects and does not affect interrupt recognition by the CPU ...
Page 96
... Freescale Semiconductor, Inc. During a CPU space cycle, bits [15:3] of the appropriate base register must be config- ured to match ADDR[23:11], as the address is compared to an address generated by the CPU. Figure 4-19 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0] are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority, and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge code ...
Page 97
... Freescale Semiconductor, Inc. weak internal pull-up drivers for each of the data lines, so that chip-select operation will be selected by default out of reset. However, the internal pull-up drivers can be overcome by bus loading effects — to insure a particular configuration out of reset, use an active device to put the data lines in a known state during reset. The base address fields in chip-select base address registers CSBAR[0:10] and chip select option regis- ters CSOR[0:10] have the reset values shown in Table 4-23 ...
Page 98
... Freescale Semiconductor, Inc. Table 4-24 CSBOOT Base and Option Register Reset Values Fields Base Address Block Size Async/Sync Mode Upper/Lower Byte Read/Write AS/DS DSACK Address Space Autovector 4.9 Parallel Input/Output Ports Fifteen SIM pins can be configured for general-purpose discrete input and output. Al- though these pins are organized into two ports, port E and port F, function assignment is by individual pin ...
Page 99
... Freescale Semiconductor, Inc. SECTION 5 CENTRAL PROCESSING UNIT The CPU32, the instruction processing module of the M68300 family, is based on the industry-standard MC68000 processor. It has many features of the MC68010 and MC68020, as well as unique features suited for high-performance controller applica- tions. This section is an overview of the CPU32. For detailed information concerning CPU operation, refer to the CPU32 Reference Manual (CPU32RM/AD) ...
Page 100
... Freescale Semiconductor, Inc. CONTROL STORE CONTROL LOGIC MICROSEQUENCER AND CONTROL ADDRESS BUS Figure 5-1 CPU32 Block Diagram 5.2 CPU32 Registers The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels. User programs can use only the registers of the user model ...
Page 101
... Freescale Semiconductor, Inc Figure 5-2 User Programming Model Figure 5-3 Supervisor Programming Model Supplement 5.2.1 Data Registers The eight data registers can store data operands 16, 32, and 64 bits and ad- dresses bits. The following data types are supported: • Bits • Packed Binary-Coded Decimal Digits • ...
Page 102
... Freescale Semiconductor, Inc. Each of data registers D7– bits wide. Byte operands occupy the low-order 8 bits; word operands, the low-order 16 bits; and long-word operands, the entire 32 bits. When a data register is used as either a source or destination operand, only the ap- propriate low-order byte or word (in byte or word operations, respectively) is used or changed ...
Page 103
... Freescale Semiconductor, Inc. 5.2.2 Address Registers Each address register and stack pointer is 32 bits wide and holds a 32-bit address. Ad- dress registers cannot be used for byte-sized operands. Therefore, when an address register is used as a source operand, either the low-order word or the entire long-word operand is used, depending upon the operation size ...
Page 104
... Freescale Semiconductor, Inc. All operations to the SR and CCR are word-size operations, but for all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege level. Refer to APPENDIX D REGISTER SUMMARY for bit/field definitions and a diagram of the status register. ...
Page 105
... Freescale Semiconductor, Inc MSB BYTE 0 BYTE 2 15 MSB 15 MSB LONG WORD 0 LONG WORD 1 LONG WORD 2 15 MSB ADDRESS 0 ADDRESS 1 ADDRESS 2 MSB = Most Significant Bit LSB = Least Significant Bit BCD 0 MSD BCD 4 MSD = Most Significant Digit LSD = Least Significant Digit Figure 5-6 Memory Operand Addressing MC68332 USER’ ...
Page 106
... Freescale Semiconductor, Inc. 5.4 Virtual Memory The full addressing range of the CPU32 on the MC68331 is 16 Mbytes in each of eight address spaces. Even though most systems implement a smaller physical memory, the system can be made to appear to have a full 16 Mbytes of memory available to each user program by using virtual memory techniques. ...
Page 107
... Freescale Semiconductor, Inc. The halted processing state is an indication of catastrophic hardware failure. For ex- ample, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. The background processing state is initiated by breakpoints, execution of special in- structions double bus fault ...
Page 108
... Freescale Semiconductor, Inc. Table 5-1 Instruction Set Summary Instruction Syntax ABCD Dn, Dn – (An), – (An) ADD Dn, <ea> <ea>, Dn ADDA <ea>, An ADDI #<data>, <ea> ADDQ #<data>, <ea> ADDX Dn, Dn – (An), – (An) AND <ea>, Dn Dn, <ea> ANDI #<data>, <ea> ANDI to CCR #<data>, CCR 1 #<data>, SR ...
Page 109
... Freescale Semiconductor, Inc. Table 5-1 Instruction Set Summary DBcc Dn, <label> DIVS/DIVU <ea>, Dn DIVSL/DIVUL <ea> <ea>, Dq <ea> EOR Dn, <ea> EORI #<data>, <ea> EORI to CCR #<data>, CCR #<data> EORI to SR EXG Rn, Rn EXT Dn Dn EXTB Dn ILLEGAL none JMP Í JSR Í LEA <ea>, An LINK An, #< ...
Page 110
... Freescale Semiconductor, Inc. Table 5-1 Instruction Set Summary RTR none RTS none SBCD Dn, Dn – (An), – (An) Scc Í #<data> 1 STOP SUB <ea>, Dn Dn, <ea> SUBA <ea>, An SUBI #<data>, <ea> SUBQ #<data>, <ea> SUBX Dn, Dn – (An), – (An) SWAP Dn TBLS/TBLU <ea>, Dn Dym : Dyn, Dn TBLSN/TBLUN < ...
Page 111
... Freescale Semiconductor, Inc. 5.8.2 Special Control Instructions Low power stop (LPSTOP) and table lookup and interpolate (TBL) instructions have been added to the MC68000 instruction set for use in controller applications. 5.8.2.1 Low Power Stop (LPSTOP) In applications where power consumption is a consideration, the CPU32 forces the de- vice into a low power standby mode when immediate processing is not required ...
Page 112
... Freescale Semiconductor, Inc. Table 5-2 Exception Vector Assignments Vector Number 16– 32–47 48–58 59–63 64–255 Each vector is assigned an 8-bit number. Vector numbers for some exceptions are ob- tained from an external device; others are supplied by the processor. The processor multiplies the vector number by four to calculate vector offset, then adds the offset to the contents of the VBR ...
Page 113
... Freescale Semiconductor, Inc. Sources of external exception include interrupts, breakpoints, bus errors, and reset re- quests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access con- trol and processor restart. ...
Page 114
... Freescale Semiconductor, Inc. causing a change in program flow. In the trace mode, a trace exception is gener- ated after an instruction is executed, allowing a debugger program to monitor the execution of a program under test. Breakpoint Instruction — An emulator may insert software breakpoints into the target code to indicate when a breakpoint has occurred. On the MC68010, MC68020, MC68030, and CPU32, this function is provided via illegal instructions, $4848– ...
Page 115
... Freescale Semiconductor, Inc. TARGET SYSTEM Figure 5-8 Bus State Analyzer Configuration 5.10.2.1 Enabling BDM Accidentally entering BDM in a non-development environment can lock up the CPU32 when the serial command interface is not available. For this reason, BDM is enabled during reset via the breakpoint (BKPT) signal. ...
Page 116
... Freescale Semiconductor, Inc. 5.10.2.2.1 External BKPT Signal Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has the same timing relationship to the data strobe trailing edge as does read cycle data. There is no breakpoint acknowledge bus cycle when BDM is entered. ...
Page 117
... Freescale Semiconductor, Inc. A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence is distinguished by a value of $FFFFFFFF in the current instruction PC other time will the processor write an odd value into this register. 5.10.2.4 BDM Commands Commands consist of one 16-bit operation word and can include one or more 16-bit extension words ...
Page 118
... Freescale Semiconductor, Inc. 5.10.2.5 Background Mode Registers BDM processing uses three special purpose registers to keep track of program context during development. A description of each follows. 5.10.2.5.1 Fault Address Register (FAR) The FAR contains the address of the faulting bus cycle immediately following a bus or address error. This address remains available until overwritten by a subsequent bus cycle ...
Page 119
... Freescale Semiconductor, Inc. CPU STATUS EXECUTION UNIT SYNCHRONIZE MICROSEQUENCER Figure 5-9 Debug Serial I/O Block Diagram The serial interface uses a full-duplex synchronous protocol similar to the serial pe- ripheral interface (SPI) protocol. The development system serves as the master of the serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from the CPU32 system clock, development system serial logic is unhindered by the oper- ating frequency of the target processor ...
Page 120
... Freescale Semiconductor, Inc S/C STATUS CONTROL BIT Figure 5-10 BDM Serial Data Word Table 5-6 CPU Generated Message Encoding Bit Command and data transfers initiated by the development system should clear bit 16. The current implementation ignores this bit; however, Freescale reserves the right to use this bit for future enhancements ...
Page 121
... Freescale Semiconductor, Inc. 5.10.5 On-Chip Breakpoint Hardware An external breakpoint input and on-chip breakpoint hardware allow a breakpoint trap on any memory access. Off-chip address comparators preclude breakpoints unless show cycles are enabled. Breakpoints on instruction prefetches that are ultimately flushed from the instruction pipeline are not acknowledged; operand breakpoints are always acknowledged ...
Page 122
... Freescale Semiconductor, Inc. 5-24 For More Information On This Product, CENTRAL PROCESSING UNIT Go to: www.freescale.com MC68332 USER’S MANUAL ...
Page 123
... Freescale Semiconductor, Inc. SECTION 6 QUEUED SERIAL MODULE This section is an overview of queued serial module (QSM) function. Refer to the QSM Reference Manual (QSMRM/AD) for complete information about the QSM. 6.1 General The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial communication interface (SCI) ...
Page 124
... Freescale Semiconductor, Inc. ity. Advanced error detection circuitry catches glitches 1/ bit time in duration. Wakeup functions allow the CPU to run uninterrupted until meaningful data is available. 6.2 QSM Registers and Address Map There are four types of QSM registers: QSM global registers, QSM pin control regis- ters, QSPI registers, and SCI registers ...
Page 125
... Freescale Semiconductor, Inc. 6.2.1.2 Freeze Operation The freeze (FRZ[1:0]) bits in the QSMCR are used to determine what action is taken by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the CPU enters background debugging mode. At the present time, FRZ0 has no effect; ...
Page 126
... Freescale Semiconductor, Inc. the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI. The port QS data direction register (DDRQS) determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output ...
Page 127
... Freescale Semiconductor, Inc. form full duplex three-wire or half duplex two-wire transfers. A variety of transfer rate, clocking, and interrupt-driven communication options are available. Serial transfer of any number of bits from eight to sixteen can be specified. Program- mable transfer length simplifies interfacing to a number of devices that require different data lengths ...
Page 128
... Freescale Semiconductor, Inc. QUEUE CONTROL BLOCK 4 QUEUE POINTER COMPARATOR DONE END QUEUE POINTER CONTROL LOGIC STATUS REGISTER CONTROL REGISTERS DELAY COUNTER PROGRAMMABLE LOGIC ARRAY Figure 6-2 QSPI Block Diagram 6.3.1 QSPI Registers The programmer's model for the QSPI consists of the QSM global and pin control reg- isters, four QSPI control registers (SPCR[0:3]), a status register (SPCR), and the 80- byte QSPI RAM ...
Page 129
... Freescale Semiconductor, Inc. 6.3.1.1 Control Registers Control registers contain parameters for configuring the QSPI and enabling various modes of operation. The CPU has read and write access to all control registers, but the QSM has read-only access to all bits except the SPE bit in SPCR1. Control regis- ters must be initialized before the QSPI is enabled to ensure defined operation ...
Page 130
... Freescale Semiconductor, Inc. D00 RR0 RR1 RR2 RECEIVE RAM RRD RRE D1E RRF WORD 6.3.2.2 Transmit RAM Data that transmitted by the QSPI is stored in this segment. The CPU normally writes one word of data into this segment for each queue command to be executed. ...
Page 131
... Freescale Semiconductor, Inc. Table 6-2 QSPI Pin Function Pin/Signal Name Mnemonic Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Slave Select Peripheral Chip Select 0 6.3.4 QSPI Operation The QSPI uses a dedicated 80-byte block of static RAM accessible by both the QSPI and the CPU to perform queued operations ...
Page 132
... Freescale Semiconductor, Inc. 6.3.5 QSPI Operating Modes The QSPI operates in either master or slave mode. Master mode is used when the MCU originates data transfers. Slave mode is used when an external device initiates serial transfers to the MCU through the QSPI. Switching between the modes is con- trolled by MSTR in SPCR0 ...
Page 133
... Freescale Semiconductor, Inc. CPU INITIALIZES QSM GLOBAL REGISTERS CPU INITIALIZES QSM PIN REGISTERS CPU INITIALIZES QSPI CONTROL REGISTERS CPU INITIALIZES CPU ENABLES QSPI Figure 6-4 Flowchart of QSPI Initialization Operation MC68332 USER’S MANUAL For More Information On This Product, BEGIN INITIALIZATION OF QSPI BY THE CPU ...
Page 134
... Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (MASTER MODE) IS QSPI DISABLED HAS NEWQP BEEN WRITTEN READ COMMAND CONTROL AND TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS ASSERT PERIPHERAL CHIP-SELECT(S) IS PCS TO SCK DELAY PROGRAMMED EXECUTE STANDARD DELAY EXECUTE SERIAL TRANSFER STORE RECEIVED DATA ...
Page 135
... Freescale Semiconductor, Inc. QSPI CYCLE BEGINS (SLAVE MODE QSPI DISABLED HAS NEWQP BEEN WRITTEN READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS IS SLAVE SELECT PIN ASSERTED EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS ...
Page 136
... Freescale Semiconductor, Inc. WRITE QUEUE POINTER TO CPTQP STATUS BITS IS CONTINUE BIT ASSERTED NEGATE PERIPHERAL CHIP-SELECT(S) IS DELAY AFTER TRANSFER ASSERTED EXECUTE STANDARD DELAY Figure 6-5 Flowchart of QSPI Master Operation (Part 3) 6-14 For More Information On This Product, B1 YES ? NO YES EXECUTE PROGRAMMED DELAY ? NO C QUEUED SERIAL MODULE Go to: www ...
Page 137
... Freescale Semiconductor, Inc QSPI DISABLED HAS NEWQP BEEN WRITTEN READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS IS SLAVE SELECT PIN ASSERTED EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS WRITE QUEUE POINTER TO CPTQP STATUS BITS ...
Page 138
... Freescale Semiconductor, Inc THIS THE YES LAST COMMAND IN THE QUEUE ? NO INCREMENT WORKING QUEUE POINTER IS HALT YES OR FREEZE ASSERTED ? NO A2 Figure 6-6 Flowchart of QSPI Slave Operation (Part 2) 6-16 For More Information On This Product, ASSERT SPIF STATUS FLAG IS INTERRUPT YES ENABLE BIT SPIFIE ...
Page 139
... Freescale Semiconductor, Inc. Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus master supplies the clock signal (SCK) to time the transfer of data. Four possible combinations of clock phase and polarity can be specified by the CPHA and CPOL bits in SPCR0. ...
Page 140
... Freescale Semiconductor, Inc. The following expressions apply to SCK baud rate: or SPBR Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its inactive state value. The DSCK field in command RAM determines the delay period from chip-select asser- tion until the leading edge of the serial clock ...
Page 141
... Freescale Semiconductor, Inc. Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to com- plete conversion. There are two transfer delay options. The user can choose to delay a standard period after serial transfer is complete or can specify a delay period. Writing a value to the DTL field in SPCR1 specifies a delay period ...
Page 142
... Freescale Semiconductor, Inc. When the proper number of bits have been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working queue pointer, and loads the next data for transfer from transmit RAM. The command pointed to by the incremented working queue pointer is executed next, unless a new value has been written to NEWQP ...
Page 143
... Freescale Semiconductor, Inc. particular application. SCK is the serial clock input in slave mode. Assertion of the ac- tive-low slave select signal SS initiates slave mode operation. Before slave mode operation is initiated, DDRQS must be written to direct data flow on the QSPI pins used. Configure the MOSI, SCK and PCS0/SS pins as inputs. The MISO pin must be configured as an output ...
Page 144
... Freescale Semiconductor, Inc. 6.3.5.4 Slave Wraparound Mode Slave wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address $ the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2. Slave wraparound operation is identical to master wraparound operation. ...
Page 145
... Freescale Semiconductor, Inc. Changing the value of SCI control bits during a transfer operation may disrupt opera- tion. Before changing register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter. TRANSMITTER BAUD RATE CLOCK H ( GENERATOR 15 SCCR1 (CONTROL REGISTER 1) ...
Page 146
... Freescale Semiconductor, Inc. RECEIVER BAUD RATE CLOCK RxD PIN BUFFER PARITY DETECT WAKEUP LOGIC 15 SCCR1 (CONTROL REGISTER 1) 15 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 6-8 SCI Receiver Block Diagram 6-24 For More Information On This Product, 16 DATA H ( RECOVERY 0 SCSR (STATUS REGISTER) QUEUED SERIAL MODULE Go to: www ...
Page 147
... Freescale Semiconductor, Inc. 6.4.1.2 Status Register The SCI status register (SCSR) contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware read/write sequence. In gen- eral, flags are cleared by reading the SCSR, then reading (receiver status bits) or writ- ing (transmitter status bits) the SCDR ...
Page 148
... Freescale Semiconductor, Inc. • Start Bit — One bit-time of logic zero that indicates the beginning of a data frame. A start bit must begin with a one-to-zero transition and be preceded by at least three receive time (RT) samples of logic one. • Stop Bit — One bit-time of logic one that indicates the end of a data frame. ...
Page 149
... Freescale Semiconductor, Inc. time (RT) sampling clock with a frequency 16 times that of the SCI baud clock. The SCI determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period. 6.4.3.4 Parity Checking The parity type (PT) bit in SCCR1 selects either even ( odd ( parity ...
Page 150
... Freescale Semiconductor, Inc. The transmission complete (TC) flag in SCSR shows transmitter shifter state. When the shifter is busy set when all shifting operations are completed not automatically cleared. The processor must clear it by first reading SCSR while TC is set, then writing new data to TDR. ...
Page 151
... Freescale Semiconductor, Inc. Receiver bit processor logic drives a state machine that determines the logic level for each bit-time. This state machine controls when the bit processor logic is to sample the RXD pin and also controls when data passed to the receive serial shifter. ...
Page 152
... Freescale Semiconductor, Inc. In some applications, CPU overhead can cause a bit-time of logic level one to occur between frames. This bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled, the receiver flags an idle line. When the idle line interrupt enable (ILIE) bit in SCCR1 is set, an interrupt request is generated when the IDLE flag is set ...
Page 153
... Freescale Semiconductor, Inc. 6.5 QSM Initialization After reset, the QSM remains in an idle state until initialized. A general sequence guide for initialization follows. A. Global 1. Configuration register (QSMCR) a. Write an interrupt arbitration priority value into the IARB field. b. Clear the FREEZE and/or STOP bits for normal operation. ...
Page 154
... Freescale Semiconductor, Inc receive a. Set the receiver (RE) and receiver interrupt (RIE) bits in SCCR1 transmit a. Set transmitter (TE) and transmitter interrupt (TIE). b. Clear the transmitter data register empty (TDRE) and transmit complete (TC) indicators by reading the serial communication interface status reg- ister (SCSR). c. Write transmit data to the serial communication data register (SCDR). ...
Page 155
... Freescale Semiconductor, Inc. SECTION 7TIME PROCESSOR UNIT The time processor unit (TPU intelligent, semi-autonomous microcontroller de- signed for timing control. Operating simultaneously with the CPU, the TPU schedules tasks, processes ROM instructions, accesses shared data with the CPU, and performs input and output. Figure 7 simplified block diagram of the TPU. ...
Page 156
... Freescale Semiconductor, Inc. 7.2 TPU Components The TPU module consists of two 16-bit time bases, sixteen independent timer chan- nels, a task scheduler, a microengine, and a host interface. In addition, a dual-port pa- rameter RAM is used to pass parameters between the module and the host CPU. 7.2.1 Time Bases Two 16-bit counters provide reference time bases for all output compare and input capture events ...
Page 157
... Freescale Semiconductor, Inc. 7.2.6 Parameter RAM Parameter RAM occupies 256 bytes at the top of the system address map. Channel parameters are organized as 128 16-bit words. Although all parameter word locations in RAM can be accessed by all channels, only 100 are normally used: channels use six parameter words, while channels 14 and 15 each use eight parameter words ...
Page 158
... Freescale Semiconductor, Inc. event service time (latency) determines TPU performance in a given application. La- tency can be closely estimated — refer to Freescale TPU Reference Manual (TPURM/ AD) for more information. 7.3.2 Channel Orthogonality Most timer systems are limited by the fixed number of functions assigned to each pin. ...
Page 159
... Freescale Semiconductor, Inc. To support changing TPU application requirements, Freescale has established a TPU function library. The function library is a collection of TPU functions written for easy as- sembly in combination with each other or with custom functions. Refer to Freescale Pro- gramming Note TPUPN00/D, Using the TPU Function Library and TPU Emulation Mode for information about developing custom functions and accessing the TPU func- tion library ...
Page 160
... Freescale Semiconductor, Inc. 7.4 Standard and Enhanced Standard Time Functions The following paragraphs describe factory-programmed time functions implemented in standard and enhanced standard TPU microcode ROM. A complete description of the functions is beyond the scope of this manual. Refer to the TPU Reference Manual (TPURM/AD) for additional information. ...
Page 161
... Freescale Semiconductor, Inc. 7.4.4 Pulse-Width Modulation (PWM) The TPU can generate a pulse-width modulation waveform with any duty cycle from zero to 100% (within the resolution and latency capability of the TPU). To define the PWM, the CPU provides one parameter that indicates the period and another param- eter that indicates the high time ...
Page 162
... Freescale Semiconductor, Inc position-synchronized pulse generator function channels can operate with a single input reference channel executing a PMA or PMM input function. The input channel measures and stores the time period between the flywheel teeth and resets TCR2 when the engine reaches a reference position. The output channel uses the pe- riod calculated by the input channel to project output transitions at specific engine de- grees ...
Page 163
... Freescale Semiconductor, Inc. allowing the latest complete accumulation (over the specified number of periods) to al- ways be available in a parameter. By using the output compare function in conjunction with PPWA, an output signal can be generated that is proportional to a specified input signal. The ratio of the input and output frequency is programmable. One or more out- put signals with different frequencies, yet proportional and synchronized to a single in- put signal, can be generated on separate channels ...
Page 164
... Freescale Semiconductor, Inc. specified number of transitions, ceasing channel activity until reinitialization. After each transition or specified number of transitions, the channel can generate a link to other channels. 7.5.3 Queued Output Match (QOM) QOM can generate single or multiple output match events from a table of offsets in pa- rameter RAM ...
Page 165
... Freescale Semiconductor, Inc. 7.5.7 Universal Asynchronous Receiver/Transmitter (UART) The UART function uses one or two TPU channels to provide asynchronous commu- nications. Data word length is programmable from bits. The function supports detection or generation of even, odd, and no parity. Baud rate is freely programmable and can be higher than 100 Kbaud. Eight bidirectional UART channels running in ex- cess of 9600 baud can be implemented ...
Page 166
... Freescale Semiconductor, Inc. 7.6.1 System Configuration Registers The TPU configuration control registers, TPUMCR and TICR, determine the value of the prescaler, perform emulation control, specify whether the external TCR2 pin func- tions as a clock source or as gate of the DIV8 clock for TCR2, and determine interrupt request level and interrupt vector number assignment ...
Page 167
... Freescale Semiconductor, Inc. DIGITAL EXTERNAL SYNCHRONIZER FILTER TCR2 PIN INT CLK /8 Figure 7-3 TCR2 Prescaler Control When the T2CG bit is set, the external TCR2 pin functions as a gate of the DIV8 clock (the TPU system clock divided by 8). In this case, when the external TCR2 pin is low, the DIV8 clock is blocked, preventing it from incrementing TCR2 ...
Page 168
... Freescale Semiconductor, Inc. 7.6.2 Channel Control Registers The channel control and status registers enable the TPU to control channel interrupts, assign time functions to be executed on a specified channel, or select the mode of op- eration or the type of host service request for the time function specified. Refer to Ta- ble 7-3 ...
Page 169
... Freescale Semiconductor, Inc. Table 7-3 Channel Priority Encodings CHX[1: 7.6.3 Development Support and Test Registers These registers are used for custom microcode development or for factory test. De- scribing the use of the registers is beyond the scope of this manual. Register descrip- tions are provided in APPENDIX D REGISTER SUMMARY. Refer to the TPU Reference Manual (TPURM/AD) for more information ...
Page 170
... Freescale Semiconductor, Inc. 7-16 For More Information On This Product, TIME PROCESSOR UNIT Go to: www.freescale.com MC68332 USER’S MANUAL ...
Page 171
... Freescale Semiconductor, Inc. SECTION 8 STANDBY RAM WITH TPU EMULATION The standby RAM module with TPU emulation capability (TPURAM) consists of a con- trol register block and a 2-Kbyte array of fast (two bus cycle) static RAM, which is es- pecially useful for system stacks and variable storage. The TPURAM responds to both program and data space accesses ...
Page 172
... Freescale Semiconductor, Inc. an address that overlaps the address of the module control register block. Writing a valid base address to TRAMBAR[15:3] clears RAMDS and enables the array. TRAMBAR can be written only once after a master reset. This prevents runaway soft- ware from accidentally re-mapping the array. Because the locking mechanism is acti- vated by the first write after a master reset, the base address field should be written in a single word operation ...
Page 173
... Freescale Semiconductor, Inc. itance, V supply ramp time, available standby voltage, and available standby DD current must be known. Assuming that the rate of change is constant as V from 0 5.5 V (nominal V period, capacitance is calculated using the following expression: Where Desired capacitance differential (Transient time of maximum differential (Available supply voltage – ...
Page 174
... Freescale Semiconductor, Inc. STANDBY RAM WITH TPU EMULATION 8-4 For More Information On This Product, Go to: www.freescale.com MC68332 USER’S MANUAL ...
Page 175
... Freescale Semiconductor, Inc. APPENDIX A ELECTRICAL CHARACTERISTICS This appendix contains electrical specification tables and reference timing diagrams. Table A-1 Maximum Ratings Num 1 Supply Voltage Input Voltage 3 Instantaneous Maximum Current Single pin limit (applies to all pins) 4 Operating Maximum Current Digital Input Disruptive Current ...
Page 176
... Freescale Semiconductor, Inc. Table A-2 Typical Ratings, 16.78 MHz Operation Num 1 Supply Voltage 2 Operating Temperature 3 V Supply Current DD RUN LPSTOP, VCO off LPSTOP, External clock, maxi f 4 Clock Synthesizer Operating Voltage 5 V Supply Current DDSYN VCO on, maximum f External Clock, maximum f LPSTOP, VCO off ...
Page 177
... Freescale Semiconductor, Inc. Table A-3 Thermal Characteristics Num 1 Thermal Resistance Plastic 132-Pin Surface Mount Plastic 144-Pin Surface Mount Thin Plastic 144-Pin Surface Mount Notes: The average chip-junction temperature (T where T = Ambient Temperature Package Thermal Resistance, Junction-to-Ambient, C INT I Watts — Chip Internal Power ...
Page 178
... Freescale Semiconductor, Inc. Table A-4 16.78 MHz Clock Control Timing (V and V DD DDSYN Num Characteristic 1 PLL Reference Frequency Range 2 System Frequency On-Chip PLL System Frequency External Clock Operation 2,3,4,5 3 PLL Lock Time 6 4 VCO Frequency 5 Limp Mode Clock Frequency SYNCR X bit = 0 ...
Page 179
... Freescale Semiconductor, Inc. Table A-4a. 20.97 MHz Clock Control Timing (V and V DD Num Characteristic 1 PLL Reference Frequency Range 2 System Frequency On-Chip PLL System Frequency External Clock Operation 2,3,4,5 3 PLL Lock Time 6 4 VCO Frequency 5 Limp Mode Clock Frequency SYNCR X bit = 0 SYNCR X bit = 1 ...
Page 180
... Freescale Semiconductor, Inc. Table A-5 16.78 MHz DC Characteristics (V and V DD Num Characteristic 1 Input High Voltage 2 Input Low Voltage 1 3 Input Hysteresis 2 4 Input Leakage Current Input-only pins High Impedance (Off-State) Leakage Current All input/output and output pins CMOS Output High Voltage I = – ...
Page 181
... Freescale Semiconductor, Inc. Table A-5a. 20.97 MHz DC Characteristics (V and V DD Num Characteristic 1 Input High Voltage 2 Input Low Voltage 1 3 Input Hysteresis 2 4 Input Leakage Current Input-only pins High Impedance (Off-State) Leakage Current All input/output and output pins CMOS Output High Voltage I = – ...
Page 182
... Freescale Semiconductor, Inc. Notes for Tables A–5 and A–5a: 1. Applies to: Port E [7:4] — SIZ[1:0], AS, DS Port F [7:0] — IRQ[7:1], MODCLK Port QS [7:0] — TXD, PCS[3:1],ÊPCS0/SS, SCK, MOSI, MISO TPUCH[15:0], T2CLK BKPT/DSCLK, IFETCH, RESET, RXD, TSTME/TSC EXTAL (when PLL enabled) 2. Input-Only Pins: EXTAL, TSTME/TSC, BKPT, T2CLK, RXD ...
Page 183
... Freescale Semiconductor, Inc. Table A-6 16.78 MHz AC Timing (V and V DD DDSYN Num Characteristic F1 Frequency of Operation (32.768 kHz crystal) 1 Clock Period 1A ECLK Period 1B External Clock Input Period 2, 3 Clock Pulse Width 2A, 3A ECLK Pulse Width 2B, 3B External Clock Input High/Low Time 4, 5 Clock Rise and Fall Time 4A, 5A Rise and Fall Time — ...
Page 184
... Freescale Semiconductor, Inc. Table A-6 16.78 MHz AC Timing (Continued) (V and V DD DDSYN Num Characteristic 30A CLKOUT Low to Data In High Impedance 31 DSACK[1:0] Asserted to Data In Valid 33 Clock Low to BG Asserted/Negated 35 BR Asserted to BG Asserted (RMC Not Asserted) 37 BGACK Asserted to BG Negated 39 BG Width Negated ...
Page 185
... Freescale Semiconductor, Inc. Table A-6a. 20.97 MHz AC Timing (V and V DD Num Characteristic F1 Frequency of Operation (32.768 kHz crystal) 1 Clock Period 1A ECLK Period 3 1B External Clock Input Period 2, 3 Clock Pulse Width 2A, 3A ECLK Pulse Width 2B, 3B External Clock Input High/Low Time 4, 5 Clock Rise and Fall Time 4A, 5A Rise and Fall Time — ...
Page 186
... Freescale Semiconductor, Inc. Table A-6a. 20.97 MHz AC Timing (Continued) (V and V DD Num Characteristic 30A CLKOUT Low to Data In High Impedance 31 DSACK[1:0] Asserted to Data In Valid 33 Clock Low to BG Asserted/Negated 35 BR Asserted to BG Asserted (RMC Not Asserted) 37 BGACK Asserted to BG Negated 39 BG Width Negated ...
Page 187
... Freescale Semiconductor, Inc. Notes for Tables A–6 and A–6a: 1.All AC timing is shown with respect to 20% V 2.Minimum system clock frequency is four times the crystal frequency, subject to specified limits. 3.When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum al- lowable t period is reduced when the duty cycle of the external clock signal varies ...
Page 188
... Freescale Semiconductor, Inc. 4 CLKOUT NOTE: Timing shown with respect to 20% and 70 NOTE: Timing shown with respect to 20% and 70% V Figure A-1 CLKOUT Output Timing Diagram 4B EXTAL NOTE: Timing shown with respect to 20% and 70% V Figure A-2 External Clock Input Timing Diagram ...
Page 189
... Freescale Semiconductor, Inc. S0 CLKOUT A20–A23 FC0–FC2 SIZ0, SIZ1 R/W DSACK0 DSACK1 D0–D15 BERR HALT BKPT Figure A-4 Read Cycle Timing Diagram MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product 14A 17 46 47A 27A to: www.freescale.com 68300 RD CYC TIM ...
Page 190
... Freescale Semiconductor, Inc. S0 CLKOUT A20–A23 FC0–FC2 SIZ0, SIZ1 R/W DSACK0 DSACK1 D0–D15 BERR HALT BKPT Figure A-5 Write Cycle Timing Diagram ELECTRICAL CHARACTERISTICS A-16 For More Information On This Product 14A 17 46 47A 27A to: www.freescale.com 68300 WR CYC TIM MC68332 USER’S MANUAL ...
Page 191
... Freescale Semiconductor, Inc. CLKOUT 6 A0–A23 FC0–FC2 SIZ0, SIZ1 R/W D0–D15 BKPT Figure A-6 Fast Termination Read Cycle Timing Diagram MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product 14B 46A 27 30 30A 29A 68300 FAST RD CYC TIM Go to: www ...
Page 192
... Freescale Semiconductor, Inc. CLKOUT 6 A0–A23 FC0–FC2 SIZ0, SIZ1 R/W D0–D15 BKPT Figure A-7 Fast Termination Write Cycle Timing Diagram ELECTRICAL CHARACTERISTICS A-18 For More Information On This Product 14B 9 12 46A 68300 FAST WR CYC TIM Go to: www.freescale.com MC68332 USER’S MANUAL ...
Page 193
... Freescale Semiconductor, Inc CLKOUT A0–A23 D0–D15 AS DS R/W DSACK0 DSACK1 BR BG BGACK Figure A-8 Bus Arbitration Timing Diagram —Active Bus Case MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product S98 47A to: www.freescale.com A5 A2 39A 33 37 68300 BUS ARB TIM ...
Page 194
... Freescale Semiconductor, Inc CLKOUT A0–A23 D0–D15 AS 47A BGACK Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case S0 CLKOUT 6 A0–A23 18 R D0–D15 BKPT NOTE: Show cycles can stretch during S42 when bus accesses take longer than two cycles due to IMB module wait-state insertion ...
Page 195
... Freescale Semiconductor, Inc CLKOUT 6 A0–A23 FC0–FC2 SIZ0, SIZ1 R/W D0–D15 NOTE: AS and DS timing shown for reference only. Figure A-11 Chip Select Timing Diagram 77 RESET D0–D15 Figure A-12 Reset and Mode Select Timing Diagram MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL ...
Page 196
... Freescale Semiconductor, Inc. Table A-7 Background Debugging Mode Timing (V = 5.0 Vdc DD Num Characteristic B0 DSI Input Setup Time B1 DSI Input Hold Time B2 DSCLK Setup Time B3 DSCLK Hold Time B4 DSO Delay Time B5 DSCLK Cycle Time B6 CLKOUT High to FREEZE Asserted/Negated B7 CLKOUT High to IFETCH High Impedance ...
Page 197
... Freescale Semiconductor, Inc. CLKOUT FREEZE BKPT/DSCLK IFETCH/DSI IPIPE/DSO Figure A-13 Background Debugging Mode Timing Diagram — CLKOUT FREEZE IFETCH/DSI Figure A-14 Background Debugging Mode Timing Diagram — MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product Serial Communication B6 B7 ...
Page 198
... Freescale Semiconductor, Inc. Table A-8 16.78 MHz ECLK Bus Timing (V = 5.0 Vdc DD Num Characteristic 2 E1 ECLK Low to Address Valid E2 ECLK Low to Address Hold E3 ECLK Low to CS Valid (CS delay) E4 ECLK Low to CS Hold E5 CS Negated Width E6 Read Data Setup Time E7 Read Data Hold Time ...
Page 199
... Freescale Semiconductor, Inc. CLKOUT 2A ECLK R/W E1 A0–A23 E3 CS E15 D0–D15 E11 D0–D15 NOTE: Shown with ECLK = system clock/8 — EDIV bit in clock synthesizer control register (SYNCR Figure A-15 ECLK Timing Diagram MC68332 ELECTRICAL CHARACTERISTICS USER’S MANUAL For More Information On This Product, ...
Page 200
... Freescale Semiconductor, Inc 5.0 Vdc 10 Num Function Operating Frequency Master Slave 1 Cycle Time Master Slave 2 Enable Lead Time Master Slave 3 Enable Lag Time Master Slave 4 Clock (SCK) High or Low Time Master 2 Slave 5 Sequential Transfer Delay Master Slave (Does Not Require Deselect) ...