MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 245

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

TCR2P — Timer Count Register 2 Prescaler Control
EMU — Emulation Control
T2CG — TCR2 Clock/Gate Control
STF — Stop Flag
SUPV — Supervisor/Unrestricted
MC68332
USER’S MANUAL
TCR2 is clocked from the output of a prescaler. If T2CG = 0, the input to the TCR2
prescaler is the external TCR2 clock source. If T2CG = 1, the input is the TPU system
clock divided by eight. The TCR2 field specifies the value of the prescaler: 1, 2, 4, or
8. Channels using TCR2 have the capability to resolve down to the TPU system clock
divided by 8. The following table is a summary of prescaler output.
In emulation mode, the TPU executes microinstructions from MCU TPURAM exclu-
sively. Access to the TPURAM module through the IMB by a host is blocked, and the
TPURAM module is dedicated for use by the TPU. After reset, this bit can be written
only once.
When the T2CG bit is set, the external TCR2 pin functions as a gate of the DIV8 clock
(the TPU system clock divided by eight). In this case, when the external TCR2 pin is
low, the DIV8 clock is blocked, preventing it from incrementing TCR2. When the exter-
nal TCR2 pin is high, TCR2 is incremented at the frequency of the DIV8 clock. When
T2CG is cleared, an external clock from the TCR2 pin, which has been synchronized
and fed through a digital filter, increments TCR2.
TCR1 Prescaler
0 = TPU and TPURAM not in emulation mode
1 = TPU and TPURAM in emulation mode
0 = TCR2 pin used as clock source for TCR2
1 = TCR2 pin used as gate of DIV8 clock for TCR2
0 = TPU operating
1 = TPU stopped (STOP bit has been asserted)
0 = Supervisor access
1 = User access
00
01
10
11
TCR2 Prescaler
00
01
10
11
Divide
By
Freescale Semiconductor, Inc.
1
2
4
8
For More Information On This Product,
Divide By
Go to: www.freescale.com
Number of
REGISTER SUMMARY
Clocks
1
2
4
8
128
256
32
64
PSCK = 0
Internal Clock
16 MHz
Rate at
Divided By
16 ms
2 ms
4 ms
8 ms
16
32
64
8
Number of
Clocks
16
32
External Clock
4
8
Divided By
PSCK = 1
1
2
4
8
16 MHz
Rate at
250 ns
500 ns
1 ms
2 ms
D-31