MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 165

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.5.7 Universal Asynchronous Receiver/Transmitter (UART)
7.5.8 Brushless Motor Commutation (COMM)
7.5.9 Frequency Measurement (FQM)
7.5.10 Hall Effect Decode (HALLD)
7.6 Host Interface Registers
MC68332
USER’S MANUAL
The UART function uses one or two TPU channels to provide asynchronous commu-
nications. Data word length is programmable from 1 to 14 bits. The function supports
detection or generation of even, odd, and no parity. Baud rate is freely programmable
and can be higher than 100 Kbaud. Eight bidirectional UART channels running in ex-
cess of 9600 baud can be implemented.
This function generates the phase commutation signals for a variety of brushless mo-
tors, including three-phase brushless direct current. It derives the commutation state
directly from the position decoded in FQD, thus eliminating the need for hall effect sen-
sors.
The state sequence is implemented as a user-configurable state machine, thus pro-
viding a flexible approach with other general applications. A CPU offset parameter is
provided to allow all the switching angles to be advanced or retarded on the fly by the
CPU. This feature is useful for torque maintenance at high speeds.
FQM counts the number of input pulses to a TPU channel during a user-defined win-
dow period. The function has single shot and continuous modes. No pulses are lost
between sample windows in continuous mode. The user selects whether to detect
pulses on the rising or falling edge. This function is intended for high speed measure-
ment; measurement of slow pulses with noise rejection can be made with PTA.
This function decodes the sensor signals from a brushless motor, along with a direc-
tion input from the CPU, into a state number. The function supports two- or three-sen-
sor decoding. The decoded state number is written into a COMM channel, which
outputs the required commutation drive signals. In addition to brushless motor appli-
cations, the function can have more general applications, such as decoding “option”
switches.
The TPU memory map contains three groups of registers:
All registers except the channel interrupt status register (CISR) must be read or written
by means of word accesses. The address space of the TPU memory map occupies
512 bytes. Unused registers within the 512-byte address space return zeros when
read.
• System Configuration Registers
• Channel Control and Status Registers
• Development Support and Test Verification Registers
Freescale Semiconductor, Inc.
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TIME PROCESSOR UNIT
7-11