MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 75

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.5.6 External Bus Arbitration
MC68332
USER’S MANUAL
The halt operation has no effect on bus arbitration (refer to 4.5.6 External Bus Arbi-
tration). However, when external bus arbitration occurs while the MCU is halted, ad-
dress and control signals go to high-impedance state. If HALT is still asserted when
the MCU regains control of the bus, address, function code, size, and read/write sig-
nals revert to the previous driven states. The MCU cannot service interrupt requests
while halted.
MCU bus design provides for a single bus master at any one time. Either the MCU or
an external device can be master. Bus arbitration protocols determine when an exter-
nal device can become bus master. Bus arbitration requests are recognized during
normal processing, HALT assertion, and when the CPU has halted due to a double
bus fault.
The bus controller in the MCU manages bus arbitration signals so that the MCU has
the lowest priority. External devices that need to obtain the bus must assert bus arbi-
tration signals in the sequences described in the following paragraphs.
Systems that include several devices that can become bus master require external cir-
cuitry to assign priorities to the devices, so that when two or more external devices at-
tempt to become bus master at the same time, the one having the highest priority
becomes bus master first. The protocol sequence is:
BR can be asserted during a bus cycle or between cycles. BG is asserted in response
to BR. To guarantee operand coherency, BG is only asserted at the end of operand
transfer. Additionally, BG is not asserted until the end of an indivisible read-modify-
write operation (when RMC is negated).
If more than one external device can be bus master, required external arbitration must
begin when a requesting device receives BG. An external device must assert BGACK
when it assumes mastership, and must maintain BGACK assertion as long as it is bus
master.
Two conditions must be met for an external device to assume bus mastership. The de-
vice must receive BG through the arbitration process, and BGACK must be inactive,
indicating that no other bus master is active. This technique allows the processing of
bus requests during data transfer cycles.
BG is negated a few clock cycles after BGACK transition. However, if bus requests are
still pending after BG is negated, the MCU asserts BG again within a few clock cycles.
This additional BG assertion allows external arbitration circuitry to select the next bus
master before the current master has released the bus.
Refer to Figure 4-14, which shows bus arbitration for a single device. The flowchart
shows BR negated at the same time BGACK is asserted.
A. An external device asserts bus request signal (BR);
B. The MCU asserts the bus grant signal (BG) to indicate that the bus is available;
C. An external device asserts the bus grant acknowledge (BGACK) signal to indi-
cate that it has assumed bus mastership.
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
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