MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 131

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6.3.4 QSPI Operation
MC68332
USER’S MANUAL
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Slave Select
Peripheral Chip Select 0
The QSPI uses a dedicated 80-byte block of static RAM accessible by both the QSPI
and the CPU to perform queued operations. The RAM is divided into three segments.
There are 16 command control bytes, 16 transmit data words, and 16 receive data
words. QSPI RAM is organized so that one byte of command control data, one word
of transmit data, and one word of receive data correspond to one queue entry, $0–$F.
The CPU initiates QSPI operation by setting up a queue of QSPI commands in com-
mand RAM, writing transmit data into transmit RAM, then enabling the QSPI. The
QSPI executes the queued commands, sets a completion flag (SPIF), and then either
interrupts the CPU or waits for CPU intervention.
There are four queue pointers. The CPU can access three of them through fields in
QSPI registers. The new queue pointer (NEWQP), in SPCR2, points to the first com-
mand in the queue. An internal queue pointer points to the command currently being
executed. The completed queue pointer (CPTQP), in SPSR, points to the last com-
mand executed. The end queue pointer (ENDQP), contained in SPCR2, points to the
final command in the queue.
The internal pointer is initialized to the same value as NEWQP. During normal opera-
tion, the command pointed to by the internal pointer is executed, the value in the inter-
nal pointer is copied into CPTQP, the internal pointer is incremented, and then the
sequence repeats. Execution continues at the internal pointer address unless the
NEWQP value is changed. After each command is executed, ENDQP and CPTQP are
compared. When a match occurs, the SPIF flag is set and the QSPI stops unless wrap-
around mode is enabled.
At reset, NEWQP is initialized to $0. When the QSPI is enabled, execution begins at
queue address $0 unless another value has been written into NEWQP. ENDQP is ini-
tialized to $0 at reset, but should be changed to show the last queue entry before the
QSPI is enabled. NEWQP and ENDQP can be written at any time. When the NEWQP
value changes, the internal pointer value also changes. However, if NEWQP is written
while a transfer is in progress, the transfer is completed normally. Leaving NEWQP
and ENDQP set to $0 causes a single transfer to occur when the QSPI is enabled.
Pin/Signal Name
Freescale Semiconductor, Inc.
For More Information On This Product,
Mnemonic
Table 6-2 QSPI Pin Function
PCS[3:1]
PCS0
MISO
MOSI
SCK
SS
QUEUED SERIAL MODULE
Go to: www.freescale.com
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Serial Data Input to QSPI
Serial Data Output from QSPI
Serial Data Output from QSPI
Serial Data Input to QSPI
Clock Output from QSPI
Clock Input to QSPI
Select Peripherals
Causes Mode Fault
Initiates Serial Transfer
Selects Peripherals
Function
6-9