MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 62

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.4.4 Misaligned Operands
4.4.5 Operand Transfer Cases
4.5 Bus Operation
4-22
Nu
10
11
12
13
NOTES:
m
1
2
3
4
5
6
7
8
9
CPU32 architecture uses a basic operand size of 16 bits. An operand is misaligned
when it overlaps a word boundary. This is determined by the value of ADDR0. When
ADDR0 = 0 (an even address), the address is on a word and byte boundary. When
ADDR0 = 1 (an odd address), the address is on a byte boundary only. A byte operand
is aligned at any address; a word or long-word operand is misaligned at an odd ad-
dress.
The largest amount of data that can be transferred by a single bus cycle is an aligned
word. If the MCU transfers a long-word operand through a 16-bit port, the most signif-
icant operand word is transferred on the first bus cycle and the least significant oper-
and word is transferred on a following bus cycle.
Table 4-13 is a summary of how operands are aligned for various types of transfers.
OPn entries are portions of a requested operand that are read or written during a bus
cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle. The following
paragraphs discuss all the allowable transfer cases in detail.
Internal microcontroller modules are typically accessed in two system clock cycles,
with no wait states. Regular external bus cycles use handshaking between the MCU
and external peripherals to manage transfer size and data. These accesses take three
system clock cycles, again with no wait states. During regular cycles, wait states can
be inserted as needed by bus control logic. Refer to 4.5.2 Regular Bus Cycles for
more information.
1. The CPU32 does not support misaligned transfers.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
Byte to 8-Bit Port (Even/Odd)
Byte to 16-Bit Port (Even)
Byte to 16-Bit Port (Odd)
Word to 8-Bit Port (Aligned)
Word to 8-Bit Port (Misaligned)
Word to 16-Bit Port (Aligned)
Word to 16-Bit Port (Misaligned)
Long Word to 8-Bit Port (Aligned)
Long Word to 8-Bit Port (Misaligned)
Long Word to 16-Bit Port (Aligned)
Long Word to 16-Bit Port
(Misaligned)
3 Byte to 8-Bit Port (Aligned)
3 Byte to 8-Bit Port (Misaligned)
Transfer Case
1
Freescale Semiconductor, Inc.
Table 4-13 Operand Transfer Cases
For More Information On This Product,
2
1
SYSTEM INTEGRATION MODULE
2
1
Go to: www.freescale.com
1
[1:0]
SIZ
01
01
01
10
10
10
10
00
10
00
10
11
11
ADDR0 DSACK
X
0
1
0
1
0
1
0
1
0
1
0
1
[1:0]
10
01
01
10
10
11
01
10
10
01
01
10
10
DATA
[15:8]
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
Read Cycles
—
—
—
DATA
[7:0]
OP0
OP1
OP0
OP1
OP0
—
—
—
—
—
—
—
—
DATA
[15:8]
(OP0)
(OP0)
(OP0)
Write Cycles
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
USER’S MANUAL
DATA
(OP0)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
[7:0]
OP0
OP1
OP0
OP1
OP0
MC68332
Cycle
Next
13
12
—
—
—
—
1
2
6
2
5
4
1