MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 237

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

PF — Parity Error
D.4.7 SCDR — SCI Data Register
D.4.8 PORTQS — Port QS Data Register
D.4.9 PQSPAR — PORT QS Pin Assignment Register
MC68332
USER’S MANUAL
15
15
15
0
0
0
0
SCDR consists of two data registers located at the same address. RDR is a read-only
register that contains data received by the SCI serial interface. Data comes into the
receive serial shifter and is transferred to RDR. TDR is a write-only register that con-
tains data to be transmitted. Data is first written to TDR, then transferred to the transmit
serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0]
contain either the first eight data bits received when SCDR is read, or the first eight
data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is con-
figured for nine-bit operation. When the SCI is configured for eight-bit operation, R8/
T8 have no meaning or effect.
PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data
present on the pins. To avoid driving undefined data, first write a byte to PORTQS,
then configure DDRQS.
Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O; set-
ting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI.
RESET:
RESET:
0 = No parity error on the received data
1 = Parity error occurred on the received data.
DDRQS — PORT QS Data Direction Register
PQSPA6 PQSPA5 PQSPA4 PQSPA3
14
14
0
0
0
13
13
0
0
0
NOT USED
12
12
0
0
0
Freescale Semiconductor, Inc.
11
11
For More Information On This Product,
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0
0
10
10
0
0
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Go to: www.freescale.com
REGISTER SUMMARY
PQSPA1 PQSPA0
9
0
0
9
0
R8/T8
U
8
8
8
0
DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0
R7/T7
PQS7
7
U
7
0
7
0
RESET:
R6/T6
PQS6
U
6
6
0
6
0
R5/T5
PQS5
U
5
5
0
5
0
R4/T4
PQS4
U
4
4
0
4
0
R3/T3
PQS3
U
3
3
0
3
0
R2/T2
PQS2
U
2
2
0
2
0
$YFFC0E
R1/T1
$YFFC15
$YFFC16
$YFFC17
PQS1
U
1
1
0
1
0
R0/T0
PQS0
D-23
0
U
0
0
0
0