MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 171

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.1 General
8.2 TPURAM Register Block
8.3 TPURAM Array Address Mapping
MC68332
USER’S MANUAL
The standby RAM module with TPU emulation capability (TPURAM) consists of a con-
trol register block and a 2-Kbyte array of fast (two bus cycle) static RAM, which is es-
pecially useful for system stacks and variable storage. The TPURAM responds to both
program and data space accesses. The TPURAM can be used to emulate TPU micro-
code ROM.
The TPURAM can be mapped to any 2-Kbyte boundary in the address map, but must
not overlap the module control registers. Refer to 8.3 TPURAM Array Address Map-
ping for more information. Data can be read or written in bytes, words or long words.
The TPURAM is powered by V
contents can be maintained by power from the V
sources is automatic.
There are three TPURAM control registers: the TPURAM module configuration regis-
ter (TRAMMCR), the TPURAM test register (TRAMTST), and the TPURAM base ad-
dress and status register (TRAMBAR). To protect these registers from accidental
modification, they are always mapped to supervisor data space.
The TPURAM control register block begins at address $7FFB00 or $FFFB00, depend-
ing on the value of the module mapping (MM) bit in the SIM configuration register
(SIMCR). SECTION 4 SYSTEM INTEGRATION MODULE contains more information
about how the state of MM affects the system.
There is a 64-byte minimum control register block size for the TPURAM module. Un-
implemented register addresses are read as zeros, and writes have no effect. Refer
to APPENDIX D REGISTER SUMMARY for the register block address map and reg-
ister bit/field definitions.
Base address and status register TRAMBAR specifies the TPURAM array base ad-
dress in the MCU memory map. TRAMBAR[15:3] specify the 13 MSBs of the base ad-
dress. The TPU bus interface unit compares these bits to address lines ADDR[23:11].
If the two match, then the low order address lines and the SIZ[1:0] signals are used to
access the RAM location in the array. The TPURAM can be mapped to any 2-Kbyte
boundary in the address map, but must not overlap the module control registers. Over-
lap makes the registers inaccessible.
The RAM disable (RAMDS) bit, the LSB of the TRAMBAR, indicates whether the
TPURAM array is active (RAMDS = 0) or disabled (RAMDS = 1). The array is disabled
coming out of reset and remains disabled if the base address field is programmed with
SECTION 8 STANDBY RAM WITH TPU EMULATION
Freescale Semiconductor, Inc.
For More Information On This Product,
STANDBY RAM WITH TPU EMULATION
Go to: www.freescale.com
DD
in normal operation. During power-down, TPURAM
STBY
input. Power switching between
8-1