MC68HC908MR8CFA Freescale Semiconductor, MC68HC908MR8CFA Datasheet - Page 104

• Manufacturer Part Number: MC68HC908MR8CFA
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR8CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

System Integration Module (SIM)
7.7 Low-Power Mode
7.7.1 Wait Mode
Technical Data
104
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a 2-step clearing mechanism — for example, a read of
one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
Executing the WAIT or STOP instruction puts the MCU in a low
power-consumption mode for standby situations. The SIM holds the
CPU in a non-clocked state. Both STOP and WAIT clear the interrupt
mask (I) in the condition code register, allowing interrupts to occur.
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
R/W
IDB
IAB
Note: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
System Integration Module (SIM)
WAIT ADDR
PREVIOUS DATA
Figure 7-12. Wait Mode Entry Timing
Figure 7-12
WAIT ADDR + 1
shows the timing for wait mode entry.
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