MC68HC711K4CFN4 Freescale Semiconductor, MC68HC711K4CFN4 Datasheet - Page 18

• Manufacturer Part Number: MC68HC711K4CFN4
• Description: IC MCU 24K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

INIT — RAM and Register Mapping
RAM[3:0] —Internal RAM Map Position
REG[3:0] —128-Byte Register Block Map Position
3.3 ROM/EPROM
18
MOTOROLA
RESET:
4-Kbyte boundary after reset, 128 bytes of the RAM are located at $0300 to $037F. Remapping is ac-
complished by writing appropriate values to the INIT register. Refer to the register and RAM mapping
examples following the memory map diagram.
When power is removed from the MCU, RAM contents may be preserved using the MODB/V
A power source (2.0 Vdc –V
Can be written only once in first 64 cycles out of reset in normal modes or at any time in special mode.
These bits determine the upper four bits of the RAM address. At reset RAM is mapped to $0000. Nor-
mally the RAM would be mapped at $0000–$02FF (768 bytes). However, the register block overlaps
the first 128 bytes of RAM, causing them to be remapped to $0300–$037F. Refer to Figure 4 and Fig-
ure 5.
These bits determine the upper four bits of the register block starting address. At reset registers are
mapped to $0000 and overlap the first 128 bytes of RAM, causing them to be remapped to $0300–
$037F. Refer to Figure 4 and Figure 5.
Standard devices have 24 kbytes of EPROM (OTPROM in a non-windowed package). Custom ROM
devices have a 24-Kbyte ROM array that is mask programmed at the factory to customer specifications.
The MC68HC11K0, MC68HC11K1, MC68L11K0, and MC68L11K1 have no ROM/EPROM. Refer to
the ordering information tables.
The ROMAD and ROMON control bits in the CONFIG register control the position and presence of
ROM/EPROM in the memory map. The ROM/EPROM can be mapped at $2000–$7FFF or $A000–
$FFFF. If it is mapped to $A000–$FFFF, vector space is included. In single-chip mode the ROM/
EPROM is forced to $A000–$FFFF (ROMAD = 1) and enabled (ROMON = 1), regardless of the value
in the CONFIG register. This ensures that there will be ROM/EPROM at the vector space. In special
test mode, the ROMON bit is forced to zero so that the ROM/EPROM is removed from the memory map.
Refer to Figure 4.
Programming EPROM requires an external 12.25 volt nominal power supply (V
plied to the XIRQ/V
Normal EPROM/OTPROM programming can be accomplished in any operating mode. Normal pro-
gramming is accomplished using the EPROM/OTPROM programming register (EPROG). The EPROG
register enables the EPROM programming voltage, controls the latching of data to be programmed, and
selects single- or multiple-byte programming.
To program the EPROM, complete the following steps using the EPROG register:
1. Set the ELAT bit in EPROG register. EELAT bit in PPROG must be cleared as it negates the
2. Write data to the desired address.
3. Turn on programming voltage to the EPROM array by setting the EPGM bit in EPROG register.
4. Delay for 2 ms or more, as appropriate.
5. Clear the EPGM bit in EPROG to turn off the programming voltage.
function of the ELAT bit.
RAM3
Bit 7
0
PPE
RAM2
6
0
pin. Three methods are used to program and verify EPROM/OTPROM.
Freescale Semiconductor, Inc.
For More Information On This Product,
DD
RAM1
) applied to this pin protects all 768 bytes of RAM.
5
0
Go to: www.freescale.com
RAM0
4
0
REG3
0
3
REG2
2
0
REG1
1
0
PPE
M68HC11 K Series
$003D
REG0
Bit 0
) that must be ap-
MC6HC11KTS/D
0
STBY
pin.