MC9S12DG128VPV Freescale Semiconductor, MC9S12DG128VPV Datasheet - Page 55

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MC9S12DG128VPV

Manufacturer Part Number
MC9S12DG128VPV
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12DG128VPV

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.25 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Function 1
Pin Name
PK[5:0]
PJ[1:0]
PM7
PM6
PM5
PM4
PE1
PE0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PK7
PJ7
PJ6
Function 2
XADDR[19:
Pin Name
BF_PSLM
BF_PERR
BF_PROK
BF_PSYN
KWJ[1:0]
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
KWJ7
KWJ6
XIRQ
ECS
IRQ
14]
Function 3
Pin Name
ROMCTL
RXCAN4
TXCAN4
RXCAN4
TXCAN4
TXCAN0
RXCAN0
MOSI1
MISO1
SCK1
SS1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Function 4
Pin Name
RXCAN4
TXCAN4
SCL
SDA
Go to: www.freescale.com
Function 5
Pin Name
MOSI0
SCK0
Powered
MC9S12DT128B Device User Guide — V01.09
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
by
PUPKE
PUPKE
Always
Always
PERH/
PERH/
PERH/
PERH/
PERH/
PERH/
PERH/
PERH/
PUCR/
PUCR/
PERM/
PERM/
PERM/
PERM/
PERJ/
PERJ/
PERJ/
PPSM
PPSM
PPSM
PPSM
CTRL
PPSH
PPSH
PPSH
PPSH
PPSH
PPSH
PPSH
PPSH
PPSJ
PPSJ
PPSJ
Up
Up
Internal Pull
Resistor
Disabled Port H I/O, Interrupt
Disabled Port H I/O, Interrupt
Disabled Port H I/O, Interrupt
Disabled Port H I/O, Interrupt
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Reset
State
Up
Up
Up
Up
Up
Up
Up
Port E Input,
Maskable Interrupt
Port E Input, Non
Maskable Interrupt
Port H I/O, Interrupt,
SS of SPI1
Port H I/O, Interrupt,
SCK of SPI1
Port H I/O, Interrupt,
MOSI of SPI1
Port H I/O, Interrupt,
MISO of SPI1
Port J I/O, Interrupt,
TX of CAN4, SCL of
IIC
Port J I/O, Interrupt,
RX of CAN4, SDA of
IIC
Port J I/O, Interrupts
Port K I/O,
Emulation Chip
Select, ROM Control
Port K I/O, Extended
Addresses
Port M I/O, BF slot
mismatch pulse, TX
of CAN4
Port M I/O, BF illegal
pulse/message
format error pulse,
RX of CAN4
Port M I/O, BF
reception ok pulse,
TX of CAN0, CAN4,
SCK of SPI0
Port M I/O, BF sync
pulse (Rx/Tx) OK
pulse o/p, RX of
CAN0, CAN4, MOSI
of SPI0
Description

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