HD64F2636F20J Renesas Electronics America, HD64F2636F20J Datasheet - Page 168

IC H8S MCU FLASH 128K 128QFP

HD64F2636F20J

Manufacturer Part Number
HD64F2636F20J
Description
IC H8S MCU FLASH 128K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2636F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Section 2 Instruction Descriptions
2.2.42 (2)
MULXS (MULtiply eXtend as Signed)
Operation
ERd
Assembly-Language Format
MULXS.W Rs, ERd
Operand Size
Word
Description
This instruction multiplies the lower 16 bits of a 32-bit register ERd (destination operand) by the
contents of a 16-bit register Rs (source operand) as signed data and stores the result in the 32-bit
register ERd. Rs can be the upper part (Ed) or lower part (Rd) of ERd. The operation performed is
16 bits
Available Registers
ERd: ER0 to ER7
Rs:
Operand Format and Number of States Required for Execution
Note: * The number of states in the H8S/2000 CPU is 21.
Notes
Rev. 4.00 Feb 24, 2006 page 152 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
R0 to R7, E0 to E7
Rs
A maximum of three additional states are required for execution of this instruction within three states
after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP)
between the MAC instruction and this instruction, this instruction will be two states longer.
The number of states may differ depending on the product. For details, refer to the relevant
microcontroller hardware manual of the product in question.
Don’t care
16 bits
MULXS (W)
ERd
16 bits
Mnemonic
MULXS.W
ERd
32 bits signed multiplication.
Multiplicand
Operands
Rs, ERd
1st byte
0
Multiplier
16 bits
Rs
1
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Previous value remains unchanged.
C: Previous value remains unchanged.
2nd byte
C
Instruction Format
cleared to 0.
cleared to 0.
I
0
UI H
3rd byte
5
Product
32 bits
U
ERd
2
N
4th byte
rs
Z
Multiply Signed
0 erd
— —
V
States
No. of
C
5*

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