HD64F2636F20J Renesas Electronics America, HD64F2636F20J Datasheet - Page 219

IC H8S MCU FLASH 128K 128QFP

HD64F2636F20J

Manufacturer Part Number
HD64F2636F20J
Description
IC H8S MCU FLASH 128K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2636F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
2.2.57 (6)
SHAL (SHift Arithmetic Left)
Operation
ERd (left arithmetic shift)
Assembly-Language Format
SHAL.L #2, ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) two bits to the left.
Bit 30 shifts into the carry flag. Bits 0 and 1 are cleared to 0.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Register direct
Addressing
Mode
SHAL (L)
Mnemonic
SHAL.L
C
ERd
MSB
Operands
b31
#2, ERd
b30
. . . . . .
1st byte
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 30.
2nd byte
F
Instruction Format
cleared to 0.
cleared to 0.
cleared to 0.
Rev. 4.00 Feb 24, 2006 page 203 of 322
I
0 erd
UI H
b1
0
Section 2 Instruction Descriptions
3rd byte
LSB
b0
0
U
N
0
4th byte
REJ09B0139-0400
Shift Arithmetic
Z
V
States
No. of
C
1

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