EG80C196EA Intel, EG80C196EA Datasheet - Page 11

• Manufacturer Part Number: EG80C196EA
• Description: IC MPU 16-BIT 5V 40MHZ 160-QFP
• Manufacturer: Intel
• Series: 80Cr

Specifications of EG80C196EA

• Core Processor: MCS 96
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SIO
• Peripherals: PWM, WDT
• Number Of I /o: 83
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 864391

4.0
Preliminary Datasheet
Table 4. Signal Descriptions (Sheet 1 of 3)
Signals
ALE
BHE#
CLKOUT
EXTINT
INST
NMI
ONCE
Name
Type
O
O
O
O
I
I
I
Address Latch Enable
This active-high output signal is asserted only during external memory cycles. ALE
signals the start of an external bus cycle and indicates that valid address information
is available on the system address/data bus.
An external latch can use this signal to demultiplex address from the address/data
bus.
Byte High Enable
During 16-bit bus cycles, this active-low output signal is asserted for word and
high-byte reads and writes to external memory. BHE# indicates that valid data is
being transferred over the upper half of the system data bus. Use BHE#, in
conjunction with A0, to determine which memory byte is being transferred over the
system bus:
BHE#
0
0
1
BHE# shares a package pin with WRH#.
† The chip configuration register 0 (CCR0) determines whether this pin functions as
Clock Output
Output of the internal clock generator. CLKOUT has a 50% duty cycle.
shares a package pin
External Interrupt
In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the
device to resume normal operation. The interrupt need not be enabled, but the pin
must be configured as a special-function input. If the EXTINT interrupt is enabled,
the CPU executes the interrupt service routine. Otherwise, the CPU executes the
instruction that immediately follows the command that invoked the power-saving
mode.
In idle mode, asserting any enabled interrupt causes the device to resume normal
operation.
Instruction Fetch
This active-high output signal is valid only during external memory bus cycles. When
high, INST indicates that an instruction is being fetched from external memory. The
signal remains high during the entire bus cycle of an external instruction fetch. INST
is low for data accesses, including interrupt vector fetches and chip configuration
byte reads. INST is low during internal memory fetches.
Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt.
NMI has the highest priority of all prioritized interrupts. Assert NMI for greater than
one state time to guarantee that it is recognized.
On-circuit Emulation
Holding ONCE during the rising edge of RESET# places the device into on-circuit
emulation (ONCE) mode. PLLEN must also be held low. This mode puts all pins into
a high-impedance state, thereby isolating the device from other components in the
system. The value of ONCE is latched when the RESET# pin goes inactive. While
the device is in ONCE mode, you can debug the system using a clip-on emulator.
To exit ONCE mode, reset the device by pulling the RESET# signal low. To prevent
inadvertent entry into ONCE mode, .
BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
A0
0
1
0
Byte(s) Accessed
both bytes
high byte only
low byte only
†
Description
80C196EA - Commercial
7