MC908AZ60AMFUER Freescale Semiconductor, MC908AZ60AMFUER Datasheet - Page 136

• Manufacturer Part Number: MC908AZ60AMFUER
• Description: IC MCU 64K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AMFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Generator Module (CGM)
10.5 CGM Registers
Three registers control and monitor operation of the CGM:
10.5.1 PLL Control Register
The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock
selector bit.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Flag Bit
PLLON — PLL On Bit
BCS — Base Clock Select Bit
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This read/write bit enables the PLL to generate a CPU interrupt request when the LOCK bit toggles,
setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF generates a CPU interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). See
Selector
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
1 = Change in lock condition
0 = No change in lock condition
1 = PLL on
0 = PLL off
PLL control register (PCTL)
PLL bandwidth control register (PBWC)
PLL programming register (PPG)
Circuit. Reset sets this bit so that the loop can stabilize as the MCU is powering up.
Address:
Do not inadvertently clear the PLLF bit. Be aware that any read or
read-modify-write operation on the PLL control register clears the PLLF bit.
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$001C
PLLIE
Bit 7
0
Figure 10-4. PLL Control Register (PCTL)
= Unimplemented
PLLF
6
0
PLLON
5
1
NOTE
BCS
4
0
3
1
1
2
1
1
1
1
1
10.3.3 Base Clock
Freescale Semiconductor
Bit 0
1
1