MCR908JK1CDWE Freescale Semiconductor, MCR908JK1CDWE Datasheet - Page 188

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MCR908JK1CDWE

Manufacturer Part Number
MCR908JK1CDWE
Description
IC MCU 1.5K FLASH 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MCR908JK1CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
14
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Break Module (BREAK)
17.4.1 Flag Protection During Break Interrupts
17.4.2 CPU During Break Interrupts
17.4.3 TIM During Break Interrupts
17.4.4 COP During Break Interrupts
17.5 Break Module Registers
Technical Data
186
The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state. (See
and see the Break Interrupts subsection for each module.)
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A break interrupt stops the timer counter.
The COP is disabled during a break interrupt when V
on the RST pin.
These registers control and monitor operation of the break module:
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
Break Module (BREAK)
7.8.3 Break Flag Control Register (BFCR)
MC68H(R)C908JL3
Freescale Semiconductor
DD
+ V
HI
is present
Rev. 1.1

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