MCR908JK3MDWE Freescale Semiconductor, MCR908JK3MDWE Datasheet - Page 81

• Manufacturer Part Number: MCR908JK3MDWE
• Description: IC MCU 4K FLASH 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCR908JK3MDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

7.4.2.2 Computer Operating Properly (COP) Reset
7.4.2.3 Illegal Opcode Reset
7.4.2.4 Illegal Address Reset
MC68H(R)C908JL3
Freescale Semiconductor
—
Rev. 1.1
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module time-out, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
every (2
should be serviced as soon as possible out of reset to guarantee the
maximum amount of time before the first time-out.
The COP module is disabled if the RST pin or the IRQ1 pin is held at
V
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1 pin. This prevents the COP from
becoming disabled as a result of external noise. During a break state,
V
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the reset status register (RSR) and
causes a reset.
If the stop enable bit, STOP, in the mask option register is logic zero, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a
reset. The SIM actively pulls down the RST pin for all internal reset
sources.
DD
DD
+ V
+ V
HI
HI
12
while the MCU is in monitor mode. The COP module can be
on the RST pin disables the COP module.
System Integration Module (SIM)
– 2
4
) 2OSCOUT cycles, drives the COP counter. The COP
System Integration Module (SIM)
Technical Data
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