MC68711E20CFNE3 Freescale Semiconductor, MC68711E20CFNE3 Datasheet - Page 81

• Manufacturer Part Number: MC68711E20CFNE3
• Description: IC MCU 8BIT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68711E20CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: M687xx
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A write collision error occurs if the SPDR is written while a transfer is in progress. Because the SPDR is
not double buffered in the transmit direction, writes to SPDR cause data to be written directly into the SPI
shift register. Because this write corrupts any transfer in progress, a write collision error is generated. The
transfer continues undisturbed, and the write data that caused the error is not written to the shifter.
A write collision is normally a slave error because a slave has no control over when a master initiates a
transfer. A master knows when a transfer is in progress, so there is no reason for a master to generate a
write-collision error, although the SPI logic can detect write collisions in both master and slave devices.
The SPI configuration determines the characteristics of a transfer in progress. For a master, a transfer
begins when data is written to SPDR and ends when SPIF is set. For a slave with CPHA equal to zero, a
transfer starts when SS goes low and ends when SS returns high. In this case, SPIF is set at the middle
of the eighth SCK cycle when data is transferred from the shifter to the parallel data register, but the
transfer is still in progress until SS goes high. For a slave with CPHA equal to one, transfer begins when
the SCK line goes to its active level, which is the edge at the beginning of the first SCK cycle. The transfer
ends in a slave in which CPHA equals one when SPIF is set. For a slave, after a byte transfer, SCK must
be in inactive state for at least 2 E-clock cycles before the next byte transfer begins.
7.7 SPI Registers
The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and data storage functions.
This sub-section provides a description of how these registers are organized.
7.7.1 SPI Control Register
SPIE — Serial Peripheral Interrupt Enable Bit
SPE — Serial Peripheral System Enable Bit
DWOM — Port D Wired-OR Mode Bit
MSTR — Master Mode Select Bit
Freescale Semiconductor
DWOM affects all six port D pins.
0 = SPI interrupt disabled
1 = SPI interrupt enabled
0 = SPI off
1 = SPI on
0 = Normal CMOS outputs
1 = Open-drain outputs
0 = Slave mode
1 = Master mode
Address:
Reset:
Read:
Write:
U = Unaffected
$0028
SPIE
Bit 7
0
Figure 7-3. SPI Control Register (SPCR)
SPE
6
0
MC68HC711D3 Data Sheet, Rev. 2.1
DWOM
5
0
MSTR
4
0
CPOL
3
0
CPHA
2
1
SPR1
U
1
SPR0
Bit 0
U
SPI Registers
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