SAF-TC1130-L150EB BB Infineon Technologies, SAF-TC1130-L150EB BB Datasheet - Page 18

• Manufacturer Part Number: SAF-TC1130-L150EB BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: FT1130L150EBBBNP; SAFTC1130L150EBBB; SP000099808

Table 2-1
Symbol
P3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
Data Sheet
Pin
A15
B15
D15
E15
G14
G15
F15
H14
C15
H15
B16
Pin Definitions and Functions (cont’d)
In
Out
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I
O
O
I
O
O
O
I
I
O
O
I
O
O
PU/
PD
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
PUC
1)
Functions
Port 3
Port 3 is a 16-bit bi-directional general purpose I/O
port which can be alternatively used for MLI1, CCU61,
SSC0/1 and OCDS Level 2 debug lines.
OCDSB_0
COUT61_3
OCDSB_1
CC61_0
OCDSB_2
COUT61_0
OCDSB_3
CC61_1
OCDSB_4
COUT61_1
OCDSB_5
CC61_2
OCDSB_6
COUT61_2
OCDSB_7
CTRAP1
SLSO0_5
OCDSB_8
CCPOS1_0
TCLK1
SLSO1_5
OCDSB_9
CCPOS1_1
TREADY1
SLSO0_6
OCDSB_10
CCPOS1_2
TVALID1
SLSO1_6
12
compare channel 1
OCDS L2 Debug Line B0
CCU61 compare channel 3 output
OCDS L2 Debug Line B1
CCU61 input/output of capture/
OCDS L2 Debug Line B2
CCU61 output of capture/compare
channel 0
OCDS L2 Debug Line B3
CCU61 input/output of capture/
OCDS L2 Debug Line B4
CCU61 output of capture/compare
channel 1
OCDS L2 Debug Line B5
CCU61 input/output of capture/
compare channel 2
OCDS L2 Debug Line B6
CCU61 output of capture/compare
OCDS L2 Debug Line B7
CCU61 trap input
SSC0 Slave Select output 5
OCDS L2 Debug Line B8
CCU61 Hall input signal 0
MLI1 transmit channel clock output
SSC1 Slave Select output 5
OCDS L2 Debug Line B9
CCU61 Hall input signal 1
MLI1 transmit channel ready input
SSC0 Slave Select output 6
OCDS L2 Debug Line B10
MLI1 transmit channel valid output
SSC1 Slave Select output 6
CCU61 Hall input signal 2
compare channel 0
channel 2
General Device Information
V1.1, 2008-12
TC1130