HFA1113IBZ Intersil, HFA1113IBZ Datasheet - Page 5

• Manufacturer Part Number: HFA1113IBZ
• Description: IC BUFFER 850MHZ 8-SOIC
• Manufacturer: Intersil

Specifications of HFA1113IBZ

• Amplifier Type: Buffer
• Number Of Circuits: 1
• Slew Rate: 2400 V/µs
• -3db Bandwidth: 850MHz
• Current - Input Bias: 25µA
• Voltage - Input Offset: 8000µV
• Current - Supply: 21mA
• Current - Output / Channel: 60mA
• Voltage - Supply, Single/dual (±): 9 V ~ 11 V, ±4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -

Application Information
Closed Loop Gain Selection
The HFA1113 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
This “buffer” operates in closed loop gains of -1, +1, or +2,
and gain selection is accomplished via connections to the
±Inputs. Applying the input signal to +IN and floating -IN
selects a gain of +1, while grounding -IN selects a gain of
+2. A gain of -1 is obtained by applying the input signal to
-IN with +IN grounded.
The table below summarizes these connections:
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
chip (0.1µF) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
For unity gain applications, care must also be taken to
minimize the capacitance to ground seen by the amplifier’s
inverting input. At higher frequencies this capacitance will
tend to short the -INPUT to GND, resulting in a closed loop
gain which increases with frequency. This will cause
excessive high frequency peaking and potentially other
problems as well.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
GAIN (A
+1
+2
-1
CL
)
+INPUT
5
(PIN 3)
GND
Input
Input
CONNECTIONS
NC (Floating)
-INPUT
(PIN 2)
Input
GND
HFA1113
avoided by placing a resistor (R
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
R
limiting system bandwidth well below the amplifier bandwidth
of 850MHz. By decreasing R
in the curves), the maximum bandwidth is obtained without
sacrificing stability. Even so, bandwidth does decrease as
you move to the right along the curve. For example, at
A
limited to 300MHz, and bandwidth drops to 100MHz at
A
Evaluation Board
The performance of the HFA1113 may be evaluated using
the HFA11XX Evaluation Board, slightly modified as follows:
The modified schematic and layout of the board are shown in
Figures 2 and 3.
To order evaluation boards (part number HFA11XXEVAL),
please contact your local sales office.
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part Number
08-350000-10.
1. Remove the 500Ω feedback resistor (R
2. a. For A
V
V
S
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
= +1, R
= +1, R
and C
connection open.
b. For A
50
45
40
35
30
25
20
15
10
resistor (R
a 0Ω resistor to GND.
5
0
0
A
L
V
S
S
form a low pass network at the output, thus
V
V
= +2
= 50Ω, C
= 5Ω, C
40
= +2, replace the 500Ω gain setting resistor with
CAPACITANCE
= +1 evaluation, remove the 500Ω gain setting
A
1
V
80
), and leave pin 2 floating.
= +1
L
L
120
= 340pF.
LOAD CAPACITANCE (pF)
= 30pF, the overall bandwidth is
160
S
as C
S
200
) in series with the output
L
increases (as illustrated
240
280 320
2
), and leave the
S
and C
July 11, 2005
360 400
FN1342.6
L