MC9S08RD32DWER Freescale Semiconductor, MC9S08RD32DWER Datasheet - Page 43

• Manufacturer Part Number: MC9S08RD32DWER
• Description: IC MCU 8BIT 32K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32DWER

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Processor Series: S08RD
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI1, SPI1
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08RG60E
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.4.1
Features of the FLASH memory include:
4.4.2
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (f
200 kHz (see
once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the
FCDIV register. One period of the resulting clock (1/f
program and erase pulses. An integer number of these timing pulses are used by the command processor
to complete a program or erase command.
Table 4-4
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Freescale Semiconductor
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FLASH Size
— MC9S08RC/RD/RE/RG60 — 63374 bytes (124 pages of 512 bytes each)
— MC9S08RC/RD/RE/RG32 — 32768 bytes (64 pages of 512 bytes each)
— MC9S08RC/RD/RE16 — 16384 bytes (32 pages of 512 bytes each)
— MC9S08RC/RD/RE8 — 8192 bytes (16 pages of 512 bytes each)
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection
Security feature for FLASH and RAM
Auto power-down for low-frequency read accesses
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
FCLK
Features
Program and Erase Times
1. Excluding start/end overhead
Section 4.6.1, “FLASH Clock Divider Register
Byte program
Byte program (burst)
Page erase
Mass erase
). The time for one cycle of FCLK is t
Parameter
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Table 4-4. Program and Erase Times
Cycles of FCLK
20,000
4000
9
4
FCLK
FCLK
) is used by the command processor to time
= 1/f
(FCDIV)”). This register can be written only
FCLK
FCLK
= 5 µs. Program and erase times
Time if FCLK = 200 kHz
. The times are shown as a number
FCLK
20 µs
100 ms
20 ms
45 µs
) between 150 kHz and
(1)
Memory
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