MCF5328CVM240 Freescale Semiconductor, MCF5328CVM240 Datasheet - Page 33

• Manufacturer Part Number: MCF5328CVM240
• Description: IC MCU 32BIT 240MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF5328CVM240

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Program Memory Size: 16KB
• Cpu Speed: 240MHz
• Embedded Interface Type: CAN, I2C, MAC, Ethernet, QSPI, UART
• Rohs Compliant: Yes
• Family Name: MPC5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 240MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.11
The MCF5329 device is compliant with industry standard USB 2.0 specification.
5.12
Control and data timing requirements for the ULPI pins are given in
All timings are measured with either a 60 MHz input clock from the USB_CLKIN pin. The USB_CLKIN needs to maintain a
50% duty cycle. Control signals and 8-bit data are always clocked on the rising edge.
The ULPI interface on the MCF5329 processor is compliant with the industry standard definition.
5.13
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
Freescale Semiconductor
ULPI_DIR/ULPI_NXT
(Output-8bit)
ULPI_DATA
ULPI_DATA
ULPI_CLK
(Input-8bit)
ULPI_STP
(Output)
USB On-The-Go
ULPI Timing Specification
SSI Timing Specifications
(Input)
Num
S1
S2
S3
S4
S5
Output delay (control out, 8-bit data out)
Setup time (control in, 8-bit data in)
SSI_MCLK cycle time
SSI_MCLK pulse width high / low
SSI_BCLK cycle time
SSI_BCLK pulse width
SSI_BCLK to SSI_FS output valid
Hold time (control in, 8-bit data in)
TSD
TSC
Parameter
MCF532x ColdFire
THC
THD
Table 19. SSI Timing – Master Modes
Description
3
2
Figure 19. ULPI Timing Diagram
Table 18. ULPI Interface Timing
®
Microprocessor Data Sheet, Rev. 5
THC, THD
TDC, TDD
TSC, TSD
Symbol
TDD
Table
18. These timings apply in synchronous mode only.
Symbol
t
t
MCLK
BCLK
−1.5
Min
—
—
1
8 × t
8 × t
45%
45%
Min
—
TDC
SYS
SYS
Max
3.0
6.0
—
55%
55%
Max
—
—
15
Electrical Characteristics
Units
ns
ns
ns
Units
t
t
MCLK
BCLK
ns
ns
ns
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