MC9328MXLVP20 Freescale Semiconductor, MC9328MXLVP20 Datasheet - Page 82

• Manufacturer Part Number: MC9328MXLVP20
• Description: IC MCU I.MX 200MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MXLr

Specifications of MC9328MXLVP20

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, Memory Stick, MMC/SD, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 225-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Functional Description and Application Information
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
Rising-edge latch data
In most of case, duty cycle is 50 / 50, therefore
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
Falling-edge latch data
4.14.2
Figure 65
and the CSI is programmed to received data on the positive edge.
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in
82
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
shows the timing diagram when the CMOS sensor output data is configured for negative edge
Non-Gated Clock Mode
VSYNC
DATA[7:0]
PIXCLK
Figure 65. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
MC9328MXL Technical Data, Rev. 8
2
Valid Data
3
Valid Data
Figure 66
4
6
5
Table
Valid Data
shows the timing diagram
36.
Freescale Semiconductor