MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 112

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Static RAM (SRAM)
The following loop initializes the entire SRAM to zero
lea.l
move.l
SRAM_INIT_LOOP:
clr.l
subq.l
bne.b
5.3.4
As noted previously, depending on the configuration defined by the RAMBAR, instruction fetch and
operand read accesses may be sent to the SRAM and cache simultaneously. If the access is mapped to the
SRAM module, it sources the read data and the unified cache access is discarded. If the SRAM is used
only for data operands, asserting the ASn bits associated with instruction fetches can decrease power
dissipation. Additionally, if the SRAM contains only instructions, masking operand accesses can reduce
power dissipation.
5-4
Power Management
Table 5-2
RAMBASE,A0
#16384,D0
(A0)+)
#1,D0
SRAM_INIT_LOOP
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Data Contained in SRAM
Both Code And Data
shows some examples of typical RAMBAR settings.
Table 5-2. Typical RAMBAR Setting Examples
Code Only
Data Only
;load pointer to SRAM
;load loop counter into D0
;clear 4 bytes of SRAM
;decrement loop counter
;if done, then exit; else continue looping
RAMBAR[7:0]
0x2B
0x35
0x21
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