MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 278

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Synchronous DRAM Controller Module
15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1)
The DACRn registers, shown in
for memory blocks 0 and 1 of the SDRAM controller. Address and timing are also controlled by bits in
DACRn.
Table 15-5
15-6
31–18
17–16
13–12
Address
Bit
15
14
11
Reset
Field
R/W
describes DACRn fields.
Name
CASL CAS latency. Affects the following SDRAM timing specifications. Timing nomenclature varies with
RE
BA
31
—
—
—
Base address register. With DCMR[BAM], determines the address range in which the associated
DRAM block is located. Each BA bit is compared with the corresponding address of the current bus
cycle. If all unmasked bits match, the address hits in the associated DRAM block. BA functions the
same as in asynchronous operation.
Reserved, should be cleared.
Refresh enable. Determines when the DRAM controller generates a refresh cycle to the DRAM block.
0 Do not refresh associated DRAM block
1 Refresh associated DRAM block
Reserved, should be cleared.
manufacturers. Refer to the SDRAM specification for the appropriate timing nomenclature:
Reserved, should be cleared.
t
t
t
t
t
command
t
RCD
CASL
RAS
RP
RWL
EP
—Last data out to precharge command
—Precharge command to
—
—SRAS assertion to SCAS assertion
,
Figure 15-3. DRAM Address and Control Register (DACRn)
t
—SCAS assertion to data out
RDL
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
ACTV
—Last data input to precharge
Uninitialized
BA
command to precharge command
Figure
Table 15-5. DACRn Field Descriptions
Parameter
IPSBAR+0x048 (DACR0); 0x050 (DACR1)
15-3, contain the base address compare value and the control bits
ACTV
18 17 16 15 14 13 12 11 10 9
command
—
Description
RE — CASL —
R/W
0
CASL= 00 CASL = 01 CASL= 10 CASL= 11
Uninitialized
1
1
2
1
1
1
Number of Bus Clocks
CBM
2
2
4
2
1
1
8
— IMRS PS IP
7
0
6
Freescale Semiconductor
3
3
6
3
1
1
5
Uninitialized
4
3
2
1
—
3
3
6
3
1
0