CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 16

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

Instruction Set Summary
The instruction set is summarized in
serves as a quick reference. If more information is needed, the
Instruction Set Summary tables are described in detail in the
Table 21. Instruction Set Summary Sorted Numerically by Opcode Order
Document #: 001-07552 Rev. *D
00 15 1
01 4
02 6
03 7
04 7
05 8
06 9
07 10 3
08
09 4
0A 6
0B 7
0C 7
0D 8
0E 9
Notes
1A
1B
1C
1D
1E
2A
2B
2C
0F 10
1F 10
10
11
12
13
14
15
16
17 10
18
19
20
21
22
23
24
25
26
27 10
28 11
29
1. Interrupt routines take 13 cycles before execution resumes at interrupt vector table.
2. The number of cycles required by an instruction is increased by one for instructions that span 256-byte boundaries in the Flash memory space.
4
4
4
6
7
7
8
9
5
4
6
7
7
8
9
5
4
6
7
7
8
9
4
6
7
7
2
2
2
2
2
3
1
2
2
2
2
2
3
3 ADC [X+expr], expr
1 PUSH X
2 SUB A, expr
2 SUB A, [expr]
2 SUB A, [X+expr]
2 SUB [expr], A
2 SUB [X+expr], A
3 SUB [expr], expr
3 SUB [X+expr], expr
1 POP A
2 SBB A, expr
2 SBB A, [expr]
2 SBB A, [X+expr]
2 SBB [expr], A
2 SBB [X+expr], A
3 SBB [expr], expr
3 SBB [X+expr], expr
1 POP X
2 AND A, expr
2 AND A, [expr]
2 AND A, [X+expr]
2 AND [expr], A
2 AND [X+expr], A
3 AND [expr], expr
3 AND [X+expr], expr
1 ROMX
2 OR A, expr
2 OR A, [expr]
2 OR A, [X+expr]
2 OR [expr], A
SSC
ADD A, expr
ADD A, [expr]
ADD A, [X+expr]
ADD [expr], A
ADD [X+expr], A
ADD [expr], expr
ADD [X+expr], expr
PUSH A
ADC A, expr
ADC A, [expr]
ADC A, [X+expr]
ADC [expr], A
ADC [X+expr], A
ADC [expr], expr
Instruction Format
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Flags
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Table 21
2D 8
2E 9
2F 10 3
30
31 4
32 6
33 7
34 7
35 8
36 9
37 10 3
38
39
3A
3B
3C
3D
4C
4D
3E 10
3F 10
4A 10
4B
4E
4F
40
41
42 10
43
44 10
45
46 10
47
48
49
50
51
52
53
54
55
56
57
58
59
9
5
5
7
8
numerically and
8
9
4
9
9
9
8
9
9
5
7
7
5
4
4
5
6
5
6
8
9
4
6
7
2
3
1
2
2
2
2
2
3
2
2
2
2
3 CMP [expr], expr
3 CMP [X+expr], expr
2 MVI A, [ [expr]++ ]
2 MVI [ [expr]++ ], A
1 NOP
3 AND reg[expr], expr
3 AND reg[X+expr], expr
3 OR reg[expr], expr
3 OR reg[X+expr], expr
3 XOR reg[expr], expr
3 XOR reg[X+expr], expr
3 TST [expr], expr
3 TST [X+expr], expr
3 TST reg[expr], expr
3 TST reg[X+expr], expr
1 SWAP A, X
2 SWAP A, [expr]
2 SWAP X, [expr]
1 SWAP A, SP
1 MOV X, SP
2 MOV A, expr
2 MOV A, [expr]
2 MOV A, [X+expr]
2 MOV [expr], A
2 MOV [X+expr], A
3 MOV [expr], expr
3 MOV [X+expr], expr
2 MOV X, expr
2 MOV X, [expr]
2 MOV X, [X+expr]
OR [X+expr], A
OR [expr], expr
OR [X+expr], expr
HALT
XOR A, expr
XOR A, [expr]
XOR A, [X+expr]
XOR [expr], A
XOR [X+expr], A
XOR [expr], expr
XOR [X+expr], expr
ADD SP, expr
CMP A, expr
CMP A, [expr]
CMP A, [X+expr]
Instruction Format
PSoC Designer Assembly Language User Guide (available on
www.cypress.com).
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
if (A=B)
Z=1
if (A<B)
C=1
Flags
[1, 2]
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
5A 5
5B 4
5C 4
5D 6
5E 7
5F 10 3
60 5
61 6
62 8
63 9
64
65
66
67
68
6C
6D
7C 13
7D
6A
6B
6E
6F
7A
7B
7E 10
7F
Ax
Bx
Cx
Dx
Ex
69
70
71
72
73
74
75
76
77
78
79
8x
9x 11
Fx 13
4
7
8
4
7
8
4
7
8
4
7
8
4
4
4
4
4
4
7
8
4
4
7
8
7
8
5
5
5
5
5
7
2
1
1
2
2
2
2
3
3
1
2
2
1
2
2 ASR [X+expr]
1 RLC A
2 RLC [expr]
2 RLC [X+expr]
1 RRC A
2 RRC [expr]
2 RRC [X+expr]
2 AND F, expr
2 OR F, expr
2 XOR F, expr
1 CPL A
1 INC A
1 INC X
2 INC [expr]
2 INC [X+expr]
1 DEC A
1 DEC X
2 DEC [expr]
2 DEC [X+expr]
3 LCALL
3 LJMP
1 RETI
1 RET
2 JMP
2 CALL
2 JZ
2 JNZ
2 JC
2 JNC
2 JACC
2 INDEX
MOV [expr], X
MOV A, X
MOV X, A
MOV A, reg[expr]
MOV A, reg[X+expr]
MOV [expr], [expr]
MOV reg[expr], A
MOV reg[X+expr], A
MOV reg[expr], expr
MOV reg[X+expr], expr
ASL A
ASL [expr]
ASL [X+expr]
ASR A
ASR [expr]
Instruction Format
CYRF69213
Z
Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
Page 16 of 77
Flags
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
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