CYRF69213-40LFXC Cypress Semiconductor Corp, CYRF69213-40LFXC Datasheet - Page 44

• Manufacturer Part Number: CYRF69213-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr
• Type: Transceiverr

Specifications of CYRF69213-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -97dBm
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Receiving: 23.4mA
• Current - Transmitting: 36.6mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2497 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1934

SPI Data Register
Table 59. SPI Data Register (SPIDATA) [0x3C] [R/W]
When an interrupt occurs to indicate to firmware that a byte of receive data is available, or the transmitter holding register is empty,
firmware has 7 SPI clocks to manage the buffers—to empty the receiver buffer, or to refill the transmit holding register. Failure to meet
this timing requirement results in incorrect data transfer.
SPI Configure Register
Table 60. SPI Configure Register (SPICR) [0x3D] [R/W]
Document #: 001-07552 Rev. *D
Bit #
Field
Read/Write
Default
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register
Bits 7:0
Bit #
Field
Read/Write
Default
Bit 7
Bit 6
Bits 5:4
Bit 3
Bit 2
Bits 1:0
Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave):
When configured for SPI, (SPI Use =
the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by firmware. For SPI
Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an input
SPI Data [7:0]
Swap
0 = Swap function disabled
1 = The SPI block swaps its use of SMOSI and SMISO. Among other things, this can be useful in implementing single
wire SPI-like communications
LSB First
0 = The SPI transmits and receives the MSB (Most Significant Bit) first
1 = The SPI transmits and receives the LSB (Least Significant Bit) first.
Comm Mode [1:0]
0 0: All SPI communication disabled
0 1: SPI master mode
1 0: SPI slave mode
1 1: Reserved
CPOL
This bit controls the SPI clock (SCLK) idle polarity
0 = SCLK idles low
1 = SCLK idles high
CPHA
The Clock Phase bit controls the phase of the clock on which data is sampled.
ious combinations of LSB First, CPOL, and CPHA
SCLK Select
This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base
CPUCLK
Swap
R/W
R/W
7
0
7
0
LSB First
R/W
R/W
6
0
6
0
1—Table
R/W
56), the input/output direction of pins P1.3, P1.5, and P1.6 is set automatically by
R/W
5
0
5
0
Comm Mode
R/W
4
0
R/W
SPIData[7:0]
4
0
R/W
CPOL
3
0
R/W
3
0
R/W
CPHA
2
0
R/W
Table 61
2
0
shows the timing for the var-
R/W
1
0
R/W
1
0
SCLK Select
CYRF69213
Page 44 of 77
R/W
0
0
R/W
0
0
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