MC13201FC Freescale Semiconductor, MC13201FC Datasheet - Page 5

• Manufacturer Part Number: MC13201FC
• Description: IC TXRX RF 2.4GHZ 32-QFN
• Manufacturer: Freescale Semiconductor

Specifications of MC13201FC

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: AMR, HID, HVAC, ISM
• Power - Output: -27dBm ~ 3dBm
• Sensitivity: -91dBm
• Voltage - Supply: 2 V ~ 3.4 V
• Current - Receiving: 37mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Operating Supply Voltage: 2.7 V
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4
The MC13201 has a data transfer mode called Packet Mode where data is buffered in on-chip Packet
RAMs. There is a TX Packet RAM and an RX Packet RAM, each of which are 64 locations by 16 bits
wide.
4.1
Figure 3
Payloads of up to 125 bytes are supported. The MC13201 adds a four-byte preamble, a one-byte Start of
Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A Frame Check
Sequence (FCS) is calculated and appended to the end of the data.
4.2
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital backend performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.
The MC13201 uses a packet mode where the data is processed as an entire packet and stored in Rx Packet
RAM. The MCU is notified that an entire packet has been received via an interrupt.
Figure 4
about -57 dBm input power which is well above 802.15.4 Standard requirements.
detection/LQI reported level versus input power.
Freescale Semiconductor
Data Transfer Mode
shows CCA reported power level versus input power. Note that CCA reported power saturates at
shows the packet structure of the MC13201 which is consistent with the 802.15.4 Standard.
Packet Structure
Receive Path Description
4 bytes
Preamble
For both graphs, the required 802.15.4 Standard accuracy and range limits
are shown. A 3.5 dBm offset has been programmed into the CCA reporting
level to center the level over temperature in the graphs.
1 byte
SFD
Figure 3. MC13201 Packet Structure
1 byte
MC13201 Technical Data, Rev. 1.3,
FLI
NOTE
125 bytes maximum
Payload Data
Figure 5
2 bytes
FCS
shows energy
5