AT86RF231-ZUR Atmel, AT86RF231-ZUR Datasheet - Page 31

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AT86RF231-ZUR

Manufacturer Part Number
AT86RF231-ZUR
Description
IC RADIO TXRX 2.4GHZ 32-VQFN
Manufacturer
Atmel
Datasheet

Specifications of AT86RF231-ZUR

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Applications
Industrial Monitoring and Control, Wireless Alarm and Security Systems
Power - Output
-17dBm ~ 3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.3mA
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
2405 MHz to 2480 MHz
Interface Type
SPI
Noise Figure
6 dB
Output Power
20 dB
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
12.3 mA
Minimum Operating Temperature
- 40 C
Modulation
OQPSK
Protocol Supported
802.15.4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
8111C–MCU Wireless–09/09
Bit
+0x04
Read/Write
Reset Value
PA_EXT_EN
R/W
7
0
IRQ_2_EXT_EN
R/W
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi purpose register to control various operating modes and
settings of the radio transceiver.
• Bit 7 - PA_EXT_EN
Refer to
• Bit 6 - IRQ_2_EXT_EN
The timing of a received frame can be determined by a separate pin. If register bit
IRQ_2_EXT_EN is set to 1, the reception of a PHR is directly issued on pin 10 (DIG2), similar to
interrupt IRQ_2 (RX_START). Note that this pin is also active even if the corresponding interrupt
event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to 0. The pin remains at
high level until the end of the frame receive procedure.
For further details refer to
• Bit 5 - TX_AUTO_CRC_ON
Refer to
• Bit 4 - RX_BL_CTRL
Refer to
• Bit [3:2] - SPI_CMD_MODE
Refer to
• Bit 1 - IRQ_MASK_MODE
The AT86RF231 supports polling of interrupt events. Interrupt polling can be enabled by register
bit IRQ_MASK_MODE. Even if an interrupt request is masked by the corresponding bit in regis-
ter 0x0E (IRQ_MASK), the event is indicated in register 0x0F (IRQ_STATUS).
Table 6-10.
6
0
Register Bit
IRQ_MASK_MODE
TX_AUTO_CRC_ON
Section 11.5 “RX/TX Indicator” on page
Section 8.2 “Frame Check Sequence (FCS)” on page
Section 11.7 “Frame Buffer Empty Indicator” on page
Section 6.3 “Radio Transceiver Status information” on page
R/W
5
1
Interrupt Polling Configuration
RX_BL_CTRL
Section 11.6 “RX Frame Time Stamping” on page
R/W
4
0
Value
0
1
R/W
3
0
Description
Interrupt polling disabled
Interrupt polling enabled
SPI_CMD_MODE
147.
R/W
2
0
IRQ_MASK_MODE
152.
85.
R/W
1
0
24.
IRQ_POLARITY
AT86RF231
150.
R/W
0
0
TRX_CTRL_1
31

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