CYWUSB6935-28SEI Cypress Semiconductor Corp, CYWUSB6935-28SEI Datasheet - Page 10

• Manufacturer Part Number: CYWUSB6935-28SEI
• Description: IC WIRELESS USB 2.4GHZ 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-28SEI

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Other names: 428-1576-5

Note:
Document 38-16008 Rev. **
Bit
7:3
2
1
0
2.
• 001–Not Valid
• 010–Not Valid
• 011–Not Valid
[2]
[2]
[2]
The following Reg 0x04, bits 2:0 values are not valid:
Name
Reserved
Code Width
Data Rate
Sample Rate The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate.
7
Addr: 0x04
Description
These bits are reserved and should be written with zeros.
The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes.
The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to inter-
ference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when double
data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as more
robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are impacted
and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1), and Sample
Rate (Reg 0x04, bit 0).
The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate of
62.5kbits/sec.
This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit (Reg
0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every 32 chips/bit
PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed in the PN code
register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the Double Data Rate
capability. When using Normal Data Rate, the raw data throughput is 32kbits/sec. Additionally, Normal Data Rate
enables the user to potentially correlate data using two differing 32 chips/bit PN codes.
Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double Data
Rate this bit is don’t care. When in the Normal Data Rate setting and choosing 12x oversampling, eliminates the ability
to receive from two different PN codes. Therefore the only time when 12x oversampling is to be selected is when a 32
chips/bit PN code is being used and there is no need to receive data from sources with two different PN codes.
1 = 32 chips/bit PN codes
0 = 64 chips/bit PN codes
1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions)
0 = Normal Data Rate - 1 bit per PN code
1 = 12x Oversampling
0 = 6x Oversampling
6
Reserved
5
PRELIMINARY
Figure 7-5. Data Rate
REG_DATA_RATE
4
3
Code Width
2
Data Rate
1
CYWUSB6935
Default: 0x00
Page 10 of 32
Sample Rate
0